At the time of their introduction in 1985, field-programmable gate arrays (FPGAs) offered limited speed and logic density. Subsequent advances in architecture and process have resulted in major improvements in speed a...
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At the time of their introduction in 1985, field-programmable gate arrays (FPGAs) offered limited speed and logic density. Subsequent advances in architecture and process have resulted in major improvements in speed and logic density. Projections for further improvements in speed, density, and cost can be developed on the basis of anticipated improvements in architectures and process. These advances will result in a narrowing of the differences between conventional custom gate arrays and FPGAs. The topics covered are evolution of FPGA architectures, process advances for FPGAs, speed, density, cost, software, markets, and applications.< >
Two approaches to the implementation of logic-gate arrays and programmablelogic are compared. It is shown that there is a large advantage of using gate arrays instead of programmablelogic device field-programmable g...
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Two approaches to the implementation of logic-gate arrays and programmablelogic are compared. It is shown that there is a large advantage of using gate arrays instead of programmablelogic device field-programmable gate arrays (PLD/FPGAs). The performance of the circuits is dramatically improved in terms of speed, power consumption, reduction in parts cost, and reliability of the circuits. Gate array (GA) technology has all of the advantages over PLD/FPGA that is has over transistor-transistor logic (TTL) circuitry. Some programmable devices have a somewhat higher level of integration than most TTL parts. Breadboarding with programmable devices and converting to GA has the disadvantage of being more costly and time consuming than designing directly with GA.< >
The fault grading methodology used for developing test vectors for the 80486 microprocessor is described. The methodology included developing a simulation model for logic verification and tests for 100% toggle coverag...
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The fault grading methodology used for developing test vectors for the 80486 microprocessor is described. The methodology included developing a simulation model for logic verification and tests for 100% toggle coverage at the RTL level, completing logic verification, developing the fault lists and optimizing them by fault collapsing, performing fault simulation on a sample of faults and in parallel simultaneously identifying/eliminating undetectable faults, performing fault simulations on complete fault lists for blocks which have high initial fault coverage, and developing new tests for blocks with low coverage. The practical issues and bottlenecks involved in quickly achieving a high fault coverage are identified. Built-in self-test features which provided a high initial fault coverage are highlighted.< >
This tool is applicable to an SRAM-based user-reprogrammable gate array based on a logic block interconnect architecture. An algorithm which led to a powerful design editor with a schematic entry dedicated to this dev...
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This tool is applicable to an SRAM-based user-reprogrammable gate array based on a logic block interconnect architecture. An algorithm which led to a powerful design editor with a schematic entry dedicated to this device structure has been developed. It determines minute logics in each block and wiring paths, both automatically and manually. The total system supports hierarchical designs by general schematic entries and functional description entries.< >
In this paper a general framework for pole assignment algorithms is described. Most of the well known output feedback pole assignment algorithms formulated in a state-space context (observers, Brasch-Pearson and Kimur...
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In this paper a general framework for pole assignment algorithms is described. Most of the well known output feedback pole assignment algorithms formulated in a state-space context (observers, Brasch-Pearson and Kimura's approaches) reduce to less than three steps of this framework. It is possible by using some more steps to exhibit more performing algorithms. Justifications of the technical results arising from the current work have already been published, only the practical implementation aspects of this framework are discussed here. It is shown that only a few basic routines are required for numerical implementation.
A minimization procedure of prime-implicant generation and covering that operates on symbolic outputs rather than binary-valued outputs is proposed for solving the output encoding problem. An exact solution to this mi...
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A minimization procedure of prime-implicant generation and covering that operates on symbolic outputs rather than binary-valued outputs is proposed for solving the output encoding problem. An exact solution to this minimization problem is also an exact solution to the encoding problem. While this covering problem is more complex than the classic unate covering problem, a single O(N factorial) logic minimization step replaces O(N factorial) minimizations. An exact algorithm is presented for state assignment by generalizing the output encoding approach to the multiple-valued input case. Preliminary experimental results are presented which indicate that medium-sized problems can be solved exactly. Computationally efficient heuristic approaches based on the exact algorithms are proposed for output encoding, state assignment, and four-level Boolean minimization.< >
We have developed a computer simulator for the asynchronous sequential circuits (ASCs) constructed by using the random access memories (RAMs). This is a generic simulator with respect to the manufacturing technology o...
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We have developed a computer simulator for the asynchronous sequential circuits (ASCs) constructed by using the random access memories (RAMs). This is a generic simulator with respect to the manufacturing technology of the RAM because all the time delays are variables and can be changed by the user. In addition, there is-no restriction on the RAM size. The simulated RAM can be programmed and then the simulator simulates the ASC with its direct feedback connections. The durations of the transition states are generated in a random fashion. The user can change the input state interactively from the keyboard and the output state of the ASC is continuously displayed on the monitor screen.
A testing procedure is given for a microprogrammed processor. The conventional procedure to generate test vectors is used instead of C-testability for the bit-slice microprocessor. The minimal complete test sequences ...
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A testing procedure is given for a microprogrammed processor. The conventional procedure to generate test vectors is used instead of C-testability for the bit-slice microprocessor. The minimal complete test sequences are calculated for the micro-sequencer and the ALU, and stored in the micro-memory. Micro-memory is implemented by an electrically erasable PLA which has the capability to test itself using a universal test set. A one-bit wide processor section is assumed. However, the method can be extended to a processor of any word length. The tests for the microsequencer and the ALU are applied from the micromemory. The response is compared against precalculated signature stored in the system memory. A parity bit is generated to indicate a fault.< >
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