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检索条件"主题词=Programmable Logic Arrays"

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Minimization of multioutput TANT networks for unlimited fan-in network model

Minimization of multioutput TANT networks for unlimited fan-...

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IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： M.A. Perkowski M. Chrzanowska-Jeske T. Shah Department of Electrical Engineering Portland State University Portland OR USA

A program for the minimization of multi-output three-level Boolean networks from NAND gates of unlimited fan-in is described. This model includes don't care states. The algorithm is fast and creates good-quality approximate solutions, and its efficiency increases with the percentage of don't cares. It has been tried on about 40 Boolean functions of not more than 14 inputs, and yielded correct results. The realized circuits (on PLH501 and PLH502 PLDs) required up to 68% (on the average 35%) less gates than the corresponding PLAs. The program can consider tradeoffs between the solution-cost and the processing speed by using various type of the source data.< >

关键词： logic devices logic circuits programmable logic arrays Minimization Boolean functions logic functions Delay logic design Input variables Timing

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Design of repairable and fully diagnosable folded PLAs for yield enhancement

Design of repairable and fully diagnosable folded PLAs for y...

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Design Automation Conference

作者： C.-L. Wey J. Ding T.-Y. Chang Department of Electrical Engineering Michigan State University East Lansing MI USA Department of Electrical Engineering National Tsing Hua University Hsinchu Taiwan

A fault-tolerant design of repairable and fully diagnosable folded PLA is presented, in which the defects can be repaired without reconfiguring the external routing. The design achieves a full diagnosability of single and multiple stuck-at, bridging, and crosspoint faults, and leads to a significant yield improvement. The physical layout and floor plan are also provided to assess the chip area.< >

关键词： programmable logic arrays Fault tolerance Circuit faults Integrated circuit yield Circuit testing Manufacturing processes Probes Very large scale integration logic design Routing

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PLA folding by partitioning

PLA folding by partitioning

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： G. Lakhani K. Kannappan Department of Computer Science Texas Tech University Lubbock TX USA LSI Logic Menlo Park CA USA

A graph-partitioning-based PLA (programmable logic array) folding algorithm is described. It is solved as a row/column reordering problem by following the approach of F.H. Wang et al. (1987). The implementation considers the area of the folded PLA as the cost function. Many experimental results show that the tool produces results superior to those produced by the PLEASURE program. The results are also about as good as those produced by a simulated-annealing-based algorithm.< >

关键词： programmable logic arrays Partitioning algorithms Simulated annealing Computer science Large scale integration Cost function Stochastic processes Constraint optimization

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An analog VLSI array processor for classical and connectionist AI

An analog VLSI array processor for classical and connectioni...

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International Conference on Application Specific Array Processors

作者： J.W. Mills C.A. Daffinger Indiana University Bloomington IN USA

The authors describe the architecture of an operational 31-cell CMOS VLSI Lukasiewicz logic array (LLA) which is regular, simple, area-efficient, and implemented with analog rather than digital processing elements. The prototype LLAs are programmed with input vectors derived from normal forms of sentences in the Lukasiewicz logic. This requires data inputs on the order of O(2/sup n/) for sentences in n implications, limits the size of the sentences that can be evaluated by a given LLA, and increases the number of pins needed on the VLSI package. The dual logic and algebraic semantics of Lukasiewicz logic allows LLAs to implement expert systems, neural networks and fuzzy logic functions. Schematic examples are given for each application, and results obtained by programming the prototype LLA as a fuzzy function generator show that the LLA implemented the notch function linearly, but with a slope that varied from that of the calculated function.< >

关键词： Very large scale integration Artificial intelligence logic arrays Fuzzy logic programmable logic arrays CMOS logic circuits Prototypes logic functions logic programming CMOS process

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A new method for the state reduction of incompletely specified finite sequential machines

A new method for the state reduction of incompletely specifi...

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European Design Automation Conference

作者： M.J. Avedillo J.M. Quintana J.L. Huertas Dpto. de Electrónica y Electromagnetismo Dpto. de Iliseno de Circuitos Análogicos Centro Nacional de Microelectrónica Universidad de Sevilla Seville Spain

A new method for the state reduction of incompletely specified finite sequential machines is proposed. Fundamental theorem of minimization theory states that, given an incomplete state table, another state table specifying the same external behavior corresponds to each closed set of compatibility classes which covers all internal states of the given table. The new heuristic algorithm builds up a closed cover for a given state table selecting maximal compatibles (MCs) one by one until both covering and closure requirements are satisfied. Near-minimal solutions are also incrementally generated. The process is dynamic as the consequences of adding a particular MC are precisely determined. The new algorithm is designed for speed and has proven to be extremely valuable in situations where fast but good optimization is required. The algorithm has been programmed and results on a wide set of machines shown.< >

关键词： Minimization Circuits Heuristic algorithms Process design Algorithm design and analysis Design optimization Silicon Complexity theory programmable logic arrays NP-complete problem

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The effectiveness of different test sets for PLAs

The effectiveness of different test sets for PLAs

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European Design Automation Conference

作者： P.C. Maxwell H.-J. Wunderlich Design Technology Laboratory Hewlett Packard Company Palo Alto CA USA Institute of Computer Design & Fault Tolerance University of Karlsruhe Karlsruhe Germany

It has been theoretically demonstrated that the single stuck-at fault model for a PLA does not cover as many faults as the single crosspoint model. What has not been demonstrated is the real relative effectiveness of test sets generated using these models. This paper presents the results of a study involving presenting a number of test sets to fabricated PLAs to determine their effectiveness. The test sets included weighted random patterns, of particular interest owing to PLAs being random resistant. Details are given of a method to generate weights, taking into account a PLA's structure.< >

关键词： programmable logic arrays Circuit faults Circuit testing System testing Fault detection Test pattern generators Laboratories Fault tolerance Design for testability Hardware

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The logic Description Generator

The Logic Description Generator

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International Conference on Application Specific Array Processors

作者： M.B. Gokhale A. Kopser S.P. Lucas R.G. Minnich

The authors describe the logic Description Generator (LDG), a design tool specifically geared to aid in the implementation of systolic algorithms on reconfigurable logic arrays. It is used to specify designs for Splash, a linear array of Xilinx chips. LDG supports the notion of a logical systolic cell, which may be repetitively layed out across a chip, and whose instances may be interconnected as a linear array. LDG also contains a reshape operator, which allows the hardware designer to place each component of the linear array at a specific location on the chip. Another feature of LDG is the ability to write general parameterized library routines. LDG allows the designer to make a simple change to a single cell and then have that change affect the configuration and layout of every other cell on the chip in a time frame comparable to the software edit-compile-test cycle. The turnaround time from textual chip specification to testing the new configuration on the Splash hardware is on the order of a half-hour, of which the LDG process contributes about five minutes. LDG is implemented in Common Lisp and runs in the Sun workstation environment. The LDG processor generates Xilinx Netlist format (XNF), which is a textual description of each logic element on the chip.< >

关键词： logic arrays logic design Reconfigurable logic Hardware programmable logic arrays Design automation Testing Sun Workstations Chip scale packaging

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68040 integer module

68040 integer module

引用

IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： K. Holden R. Eisele M. Kobe J. Raleigh T. Spohrer Microprocessor Products Group (OE38) Motorola Inc. Austin TX USA

The central CPU for the 68040 processor is the integer unit (IU). The IU contains multiple 32-bit data and address paths with heavily pipelined instruction execution control for improved performance. Frequently used instructions and addressing modes have been optimized for single cycle execution. Additionally, independent control for each pipe state yields increased throughput. Implementation of control structures for increased performance is presented, with emphasis on design trade-offs for automated logic synthesis versus full custom, hand crafted circuits. The impact of the integration of test logic on behavioral descriptions and control logic testing strategy are discussed.< >

关键词： Clocks programmable logic arrays Counting circuits Decoding Automatic control logic testing Prefetching Kirk field collapse effect Microprocessors Central Processing Unit

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A high performance SIMD processor for binary image processing

A high performance SIMD processor for binary image processin...

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Custom Integrated Circuits Conference (CICC)

作者： J.-D. Legat P. De Muelenaere Image Recognition Integrated Systems S. A. Louvain-la-Neuve Belgium

A high-performance single-instruction, multiple-data (SIMD) processor based on a full-custom VLSI chip has been designed for binary image processing applications. This dedicated IC has been fabricated in a 3- mu m NMOS technology and contains 48000 transistors. The architecture of the processor is described, and the chip description, which includes an original organization for both the data path and image memories, is highlighted. The processor is fully operational. It is used in applications like filtering, skeletonization, feature extraction, document processing, and optical character recognition.< >

关键词： Image processing Arithmetic Circuits Computer architecture Registers programmable logic arrays programmable logic devices Image recognition MOS devices Parallel processing

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An ultra high speed ECL programmable logic device

An ultra high speed ECL programmable logic device

引用

Bipolar Circuits and Technology Meeting

作者： F. Ki R. Bachireddy D. Jeong S. Cheng T. Nguyen Philips Components-Signetics Company Sunnyvale CA USA

An oxide-isolated programmable logic device (PLD) designed with emitter-coupled logic (ECL) performing beyond 200 MHz is described. This 100KH/100K compatible product is configurable, via standard fuse programming, to accept up to 20 inputs and have 8 outputs which are individually programmable to be combinatorial/registered, with/without feedback and active high/active low.< >

关键词： programmable logic devices Fuses logic devices programmable logic arrays Output feedback logic arrays Circuit testing logic design Circuit synthesis Voltage

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