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检索条件"主题词=Programmable Logic Arrays"

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Building blocks for a new generation of application specific computing systems

Building blocks for a new generation of application specific...

引用

International Conference on Application Specific Array Processors

作者： B. Baxter G. Cox T. Gross H.T. Kung D.O. O'Hallaron C. Peterson J. Webb P. Wiley School of Computer Science Carnegie Mellon University Pittsburgh PA USA Intel Corporation Hillsboro OR USA

The iWarp processor, which integrates both communication and computation functions on a single VLSI component, is described. The iWarp component and subsystems including it are powerful building blocks for constructing a new generation of application-specific computing systems. These special-purpose systems can achieve very high performance, while maintaining a high degree of flexibility to address different needs of an application. In particular, iWarp systems deliver high computation bandwidth (up to 20 GFLOPS for a 1024 cell system), as well as high communication bandwidth (320 Mbytes/s per cell). Programming these systems is assisted by modern tools such as optimizing compilers and parallel program generators.< >

关键词： Computer applications Application software Bandwidth Hardware Costs Very large scale integration Radar applications programmable logic arrays Contracts Process design

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A 3.6 ns 1 Kb ECL I/O BiCMOS UV EPROM

A 3.6 ns 1 Kb ECL I/O BiCMOS UV EPROM

引用

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： D. Smith J. Zeiter T. Bowman J. Rahm B. Kertis A. Hall S. Natan L. Sanderson R. Tromp J. Tsang Motorola Inc. Chandler AZ USA National Semiconductor Corporation Puyallup WA USA

A 1 K-density EPROM with input and output levels available in ECL (emitter-coupled logic) 100 K or 10 K with a masking option is described. TTL (transistor-transistor logic) I/O (input/output)-compatible programming and verify modes allow the memory array to be programmed with standard EPROM (erasable programmable read-only memory) hardware and software. The EPROM is essentially two devices in one. It is an ECL ROM (read-only memory) with a high-speed ECL read path. The die can be configured to 100 K or 10 K ECL I/O level with a metal mask option. It is also a UV erasable and testable CMOS EPROM. The EPROM uses a standard TTL I/O programmer for programming and verification.< >

关键词： BiCMOS integrated circuits EPROM logic programming logic devices programmable logic arrays Software standards PROM Hardware Read only memory Testing

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An efficient and flexible architecture for high-density gate arrays

An efficient and flexible architecture for high-density gate...

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IEEE International Conference on Solid-State Circuits (ISSCC)

作者： H. Veendrick D. van den Elshout D. Harberts T. Brand Phillips Res. Labs. Eindhoven Netherlands

The properties and performance of high-density gate arrays (HDGAs) are largely determined by the structure on which logic and memory functions are mapped. An architecture for an effective implementation of these functions is presented. All architecture in which each basic cell provides three nMOS and three pMOS transistors is given. Both nMOS and pMOS transistors share a common gate. The advantages of such an architecture can be fully exploited in memory and logic array structures like ROM, RAM, and PLA. Triple-metal BiCMOS processes are at present used to implement HDGAs. Replacing the expensive third metal layer with a TiSi/sub 2/ layer increases the silicon cost and processing time by no more than 5%. These straps are used to bridge only short distances, such as those within logic cells. They are also used for connecting transistors in parallel for increased driving capability. To show the benefits of the common-gate architecture, a 10*10-b fully pipelined multiplier was designed in custom standard cells using commercially available place-and-route software and then in an HDGA architecture.< >

关键词： logic arrays MOS devices MOSFETs Computer architecture Random access memory Read only memory Read-write memory programmable logic arrays BiCMOS integrated circuits Silicon

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Affordable ASIC design

Affordable ASIC design

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Annual IEEE International Conference and Exhibit ASIC

作者： J. Tanner A. Adke D.H. Lipin Tanner Research Inc. Pasadena CA USA

Recent advances in design hardware, software, and prototypes that allow affordable ASIC design are discussed. The topics discussed include economics of ASIC use and fabrication, affordable design platforms, affordable design tools, traditional gate array and standard cell technologies, field programmable gate arrays, affordable prototypes through multi-project wafers, and affordable volume production.< >

关键词： Application specific integrated circuits Costs Field programmable gate arrays Production Workstations programmable logic arrays Design automation Fabrication Prototypes Software prototyping

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Test generation for hybrid iterative logic arrays

Test generation for hybrid iterative logic arrays

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： A. Chatterjee J.A. Abraham General Electric Research and Development Center Schenectady NY University of Texas Austin

The test generation problem for hybrid iterative logic arrays (ILAs) which are constructed from ILAs of different types of cells by interconnecting them along their boundaries to realize a complex combinational function is discussed. The test generation problem for hybrid ILAs is complicated by the presence of different types of cell functions that affect test controllability and observability in different ways. For an array to be testable with a fixed number of test vectors irrespective of its size (C-testable), each of the individual constituent ILAs must satisfy certain rigid conditions that make test generation a difficult task. A graphical model is presented for test computation, and it is shown how this model can be used very effectively to generate efficient tests sets for hybrid ILAs.< >

关键词： logic testing logic arrays Hybrid power systems Circuit testing Integrated circuit interconnections Combinational circuits programmable logic arrays Research and development Jacobian matrices Controllability

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An efficient logic block interconnect architecture for user-reprogrammable gate array

An efficient logic block interconnect architecture for user-...

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Custom Integrated Circuits Conference (CICC)

作者： K. Kawana H. Keida M. Sakamoto K. Shibata I. Moriyama LSI Research Center Kawasaki Steel Corporation Chiba Japan

A novel architecture for an SRAM-based user-reprogrammable gate array which consists of programmable logic elements (PLEs), switching stations (SSs), wirings, and input/output blocks (IOBs) is discussed. The SS is designed to connect its neighboring PLEs and/or IOBs through only one NMOS pass transistor to maintain a sufficient signal level and reduce the delay in signal propagation. Hidden interconnection networks which directly merge neighboring PLEs were adopted to expand the number of inputs and product terms of combinational logic, and allow the construction of a parallel-to-serial/serial-to-parallel converter without using SSs. A fabricated CMOS prototype chip includes an 8 Kbit 50 ns temporary storage memory which is programmable to the random access mode or the FIFO mode with a word length of 4 bit or 8 bit.< >

关键词： logic arrays programmable logic arrays logic devices programmable logic devices Flip-flops Circuits Wiring Random access memory Switches Testing

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Chortle: a technology mapping program for lookup table-based field programmable gate arrays

Chortle: a technology mapping program for lookup table-based...

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Design Automation Conference

作者： R.J. Francis J. Rose K. Chung Department of Electrical Engineering University of Toronto ONT Canada

An algorithm is described for technology mapping of combinational logic into field programmable gate arrays that use lookup table memories to realize combinational functions. It is difficult to map into lookup tables using previous techniques because a single lookup table can perform a large number of logic functions and prior approaches require each function to be instantiated separately in a library. The new algorithm, implemented in a program called Chortle, uses the fact that a K-input lookup table can implement any Boolean function of K inputs and so does not require a library-based approach. Chortle takes advantage of this complete functionality to evaluate all possible decompositions of the input Boolean network nodes. It can determine the optimal (in area) mapping for fanout-free trees of combinational logic. In comparison with the MIS II technology mapper, on MCNC-89 logic Synthesis benchmarks Chortle achieves superior results in significantly less time.< >

关键词： Table lookup Field programmable gate arrays programmable logic arrays logic devices Libraries Boolean functions logic functions Vegetation mapping logic design Network synthesis

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Computer-based diagnostics for integrated manufacturing systems

Computer-based diagnostics for integrated manufacturing syst...

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International Conference on Computer Integrated Manufacturing

作者： J.H. Graham S.M. Alexander Speed Scientific School University of Louisville Louisville KY USA

Results of a research project which focused on the efficient detection and diagnosis of process faults in integrated manufacturing systems are described. This project attempted to investigate theoretical advancements in the development of a hybrid reasoning scheme for manufacturing diagnostics and to pursue applications to actual manufacturing diagnostic problems. The final implementation goal is a stand-alone computer-based diagnostic workstation which can interact with a programmable logic controller to give diagnostic advice to operating and maintenance personnel. An initial implementation of the diagnostics system has been created using an object-oriented knowledge-engineering environment on a Symbolics 3640 workstation.< >

关键词： Computer aided manufacturing Integrated manufacturing systems Workstations Fault diagnosis Costs Humans Fault detection Manufacturing systems Application software programmable logic arrays

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logic synthesis for programmable logic devices

Logic synthesis for programmable logic devices

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IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： T.-T. Hwang R.M. Owens M.J. Irwin Department of Computer Sciences Pennsylvania State University University Park PA USA

The use of communication complexity based logic synthesis when configuring programmable logic devices (PLDs) is discussed. Configuration of a PLD involves the two processes of logic synthesis and logic embedding. Since the allowable PLD logic primitives usually include a very large number of gates, the processes of logic synthesis and technology mapping cannot be completely decoupled as they normally are in traditional logic synthesis systems. The proposed communication-complexity-based logic synthesis tool has the advantage of not completely decoupling these two processes. It is more suited to PLD configuring than other multilevel logic synthesis methods.< >

关键词： programmable logic devices logic devices programmable logic arrays Switches Wires Very large scale integration Complexity theory Random access memory Computer science Helium

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A program for exact synthesis of three-level NAND networks

A program for exact synthesis of three-level NAND networks

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： M.A. Perkowski J. Liu Department of Electrical Engineering Portland State University Portland OR USA Mr. Liu's research was partially funded IEEE I CM Design Auromarion Award

A program is described for exact minimization of three-level combinational functions from NAND (NOR) gates. This algorithm generalizes the well-known approaches of TANT synthesis in the following ways: the function is multioutput, it includes don't cares, and any subset of variables can be available in only complemented form, or in both affirmative and complemented forms. The number of PP-implicants that can be used for exact minimum solution is reduced as a result of proving some theorems.< >

关键词： Network synthesis programmable logic arrays Circuit synthesis logic design Minimization methods logic circuits Algorithm design and analysis logic gates Design methodology Iterative methods

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