A survey of recent developments in the implementation of multivalued logic circuits using charge-coupled device technology is presented. A set of basic logic gate structures which is suitable for synthesis of both bin...
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A survey of recent developments in the implementation of multivalued logic circuits using charge-coupled device technology is presented. A set of basic logic gate structures which is suitable for synthesis of both binary and multivalued functions is defined. Techniques for synthesis of one- and two-variable functions is considered in detail. A special case of threshold functions is emphasised. Finally, realisation of multivalued functions in terms of programmable logic arrays is described.
A set of expert-system modules for designing easily testable VLSI circuits called DFT Expert is described. DFT Expert operates at the register-transfer level of circuit description, classifying circuit components into...
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A set of expert-system modules for designing easily testable VLSI circuits called DFT Expert is described. DFT Expert operates at the register-transfer level of circuit description, classifying circuit components into data transporters (DTs) and data processors (DPs). It identifies DPs and DTs, selects a test method, configures global design for test (DFT), and generates test schedules. DFT Expert's ability to test a practical circuit is demonstrated.
A BiCMOS programmablelogic sequencer with a maximum operating frequency of 76 MHz at a power dissipation of 370 mW has been developed. The device is organized as 16 inputs, 48 product terms, and eight registered outp...
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A BiCMOS programmablelogic sequencer with a maximum operating frequency of 76 MHz at a power dissipation of 370 mW has been developed. The device is organized as 16 inputs, 48 product terms, and eight registered outputs. The excellent speed power performance and TTL/CMOS compatibility were realized by an optimized circuit design coupled with an advanced BiCMOS process. The process features 13-GHz bipolar transistors, 1- mu m CMOS, TiW fuses, poly resistors, three-layer metal, and single-layer polycide. Bipolar devices are used in areas that utilize their strengths such as high current drivers, small-signal sensing, and precise current sources. CMOS is used in other areas to conserve layout size and power.< >
Graph theoretic properties of the PLA folding problem which not only give insight into the various folding problems but also provide efficient algorithms for solving the problems are presented. This work is based on t...
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Graph theoretic properties of the PLA folding problem which not only give insight into the various folding problems but also provide efficient algorithms for solving the problems are presented. This work is based on the transformation of the PLA into graphs where cliques (completely connected subgraphs) in the graphs correspond to PLA folding sets. A simple heuristic technique known as the greedy algorithm can often identify near-maximum cliques in polynomial time. Experimental data show that this technique is extremely effective when applied to the graphs which generally arise in folding. Variations of the general folding problem such as bipartite folding and constrained folding are addressed.< >
Algorithms are presented for Boolean decomposition, which can be used to decompose a programmablelogic array (PLA) into a set of smaller interconnected PLAs such that the overall area of the resulting logic network, ...
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Algorithms are presented for Boolean decomposition, which can be used to decompose a programmablelogic array (PLA) into a set of smaller interconnected PLAs such that the overall area of the resulting logic network, deemed to be the sum of the areas of the constituent PLAs, is minimized. These algorithms can also be used to identify good Boolean factors which can be used as strong divisors during the logic optimization to reduce the literal counts/area of general multilevel logic networks. Excellent results have been obtained.< >
It is suggested that a structured, user-friendly, cost-effective tool for rapid implementation of VLSI circuits which encourages students to participate directly in research projects is the key component in digital in...
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It is suggested that a structured, user-friendly, cost-effective tool for rapid implementation of VLSI circuits which encourages students to participate directly in research projects is the key component in digital integrated circuit (IC) education. The authors introduce their VLSI education activities, with emphasis on the presentation of path-programmablelogic (PPL) design methodology as well as a short description of a representative student project. Students using PPL are able to implement MOS or GaAs VLSI circuits with several thousand to over 100000 transistors in a few weeks. They have designed and built numerous VLSI architectures and computer systems which play an influential role in various research areas.< >
Upper and lower bounds are shown for the average number of product terms required in the minimal realization, as a function of the number of nonzero output values. The variance, in addition to the bounds, allows concl...
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Upper and lower bounds are shown for the average number of product terms required in the minimal realization, as a function of the number of nonzero output values. The variance, in addition to the bounds, allows conclusions to be drawn about how PLA size determines the set of realizable functions. Although the bounds are most accurate when there are few nonzero values, they are adequate for analyzing commercially available PLAs. The analysis shows that, for all but one commercially available PLA, the number of nonzero values is a statistically meaningful criterion for determining whether or not a given function is likely to be realized.
It is well known that a large number of errors in VLSI circuits are unidirectional in nature. J.M. Borden (Inf. Control, vol.53, p.66-73, April 1982) has studied a code for detecting only t, not all, unidirectional er...
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It is well known that a large number of errors in VLSI circuits are unidirectional in nature. J.M. Borden (Inf. Control, vol.53, p.66-73, April 1982) has studied a code for detecting only t, not all, unidirectional errors. For a code to be utilized in a self-checking system, a self-checking checker must exist for it. The totally self-checking (TSC) checker is one such checker. Many designs for TSC checkers exist for m-out-of-n codes. However, no work has been reported on the design of a TSC checker for Borden's code. The author presents such a design. They believe that this design may lead to greater applicability of Borden's code to self-checking systems.< >
An inherent problem in the use of simulators for the determination of capacitance in VLSI circuits is the verification of the reliability of the simulation. The problem is due to the numerical approximations made in o...
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An inherent problem in the use of simulators for the determination of capacitance in VLSI circuits is the verification of the reliability of the simulation. The problem is due to the numerical approximations made in order to achieve a versatile simulation. The Schwarz-Christoffel transformation provides theoretically exact simulation of a limited class of problems consisting of two odd shaped conductors embedded in a uniform dielectric. It is proposed that the Schwarz-Christoffel technique can be used to calibrate simulators designed for more general problems.< >
Presents a complete fault-tolerant programmablelogic array (PLA) design that includes both fault diagnosability and repairability. The proposed PLA design is capable of detecting, locating, and repairing single and m...
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Presents a complete fault-tolerant programmablelogic array (PLA) design that includes both fault diagnosability and repairability. The proposed PLA design is capable of detecting, locating, and repairing single and multiple stuck-at, bridging, and crosspoint faults. The results of this study show that the total augmented area overhead for both repair and fault diagnosis is nearly 15 to 25 percent over the original PLA, but the chip yield can be improved significantly.< >
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