A novel, systematic approach to sequential MOS circuit design is described. The approach aims at minimizing the number of transistors needed to implement a given switching function. The techniques used are based on th...
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A novel, systematic approach to sequential MOS circuit design is described. The approach aims at minimizing the number of transistors needed to implement a given switching function. The techniques used are based on the switching network logic (SNL) approach, which was previously introduced as a systematic method of designing MOS combinational logic circuits. The authors extend the approach to sequential MOS circuit design. Examples are given to show that the proposed method reduces the number of MOSFETs as compared to existing design methods. A CAD (computer-aided design) program based on the SNL approach is presented as a finite state machine generator.< >
The design and characterization of single-poly erasable programmable read-only memory (EPROM) cells in a standard CMOS p-well technology are discussed. Process-compatible high-voltage drivers for programming the cells...
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The design and characterization of single-poly erasable programmable read-only memory (EPROM) cells in a standard CMOS p-well technology are discussed. Process-compatible high-voltage drivers for programming the cells are presented. A memory array is implemented to illustrate the integration of the cells with standard logic circuitry.< >
An architecture for electrically configurable gate arrays using a two-terminal antifuse element is described. The architecture is extensible, and can provide a level of integration comparable to mask-programmable gate...
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An architecture for electrically configurable gate arrays using a two-terminal antifuse element is described. The architecture is extensible, and can provide a level of integration comparable to mask-programmable gate arrays. This is accomplished by using a conventional gate array organization with rows of logic modules separated by wiring channels. Each channel contains segmented wiring tracks. The overhead needed to program the antifuses is minimized by an addressing scheme that utilizes the wiring segments, pass transistors between adjacent segments, shared control lines, and serial addressing circuitry at the periphery of the array. This circuitry can also be used to test the device prior to programming and observe internal nodes after programming. By providing sufficient wiring tracks segmented into carefully chosen lengths and a logic module with a high degree of symmetry, fully automated placement and routing is facilitated.< >
The cluster finding module (CFM) is part of the UA1 trigger processor. The CFM detects and counts two-dimensional clusters of electromagnetic particles. This process requires 75 ns for detection of either isolated or ...
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The cluster finding module (CFM) is part of the UA1 trigger processor. The CFM detects and counts two-dimensional clusters of electromagnetic particles. This process requires 75 ns for detection of either isolated or nonisolated clusters and 75 ns to count them. This is equivalent to a peak computational rate of 11000 MIPS (million instructions per second) per module (3000 MIPS average). The required high logic density and speed are achieved by using programmable array logic devices within a pipelined system. The design has been strongly influenced by the need for in-situ computer testing.< >
Laser-diffused diode link (LDL) process makes possible a direct connection between devices at the substrate level, thus giving more flexibility to the overall system design. The electrical properties of these diode li...
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Laser-diffused diode link (LDL) process makes possible a direct connection between devices at the substrate level, thus giving more flexibility to the overall system design. The electrical properties of these diode links are studied. Calculations based on a model for the resistance agree well with available experimental data. This model also provides physical insight on previously undetermined material properties such as the dopant diffusivity in the melt as a function of temperature.< >
作者：
SASAO, TDept. of Comput. Sci. & Electron.
Kyushu Inst. of Technol. Iizuka Japan Abstract Authors References Cited By Keywords Metrics Similar Download Citation Email Print Request Permissions
A description is given of the design and analysis of three types of multivalued PLAs (programmable logic arrays). Type 1 PLAs realize functions directly in the form of the max of min of literal functions and constants...
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A description is given of the design and analysis of three types of multivalued PLAs (programmable logic arrays). Type 1 PLAs realize functions directly in the form of the max of min of literal functions and constants. In Type 2 PLAs, the body of the PLA is binary and the output is encoded as a multiple-valued logic value. Type 3 PLAs are the same as type 2 PLAs except for the use of 2-bit decoders and a permutation network on the input. Using the number of columns required to realize a given function as a measure to compare PLAs, it is shown that type 3 PLAs are superior to type 2, which in turn are superior to type 1
The function of a programmablelogic array (PLA) was implemented using a microcomputer. The equipment is suitable for use in laboratories because it is electrically programmable, easy to be realized and maintained, an...
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The function of a programmablelogic array (PLA) was implemented using a microcomputer. The equipment is suitable for use in laboratories because it is electrically programmable, easy to be realized and maintained, and has sufficient capacity. It has been used for implementing fixed-point arithmetic algorithms, a subject of a laboratory course given to computer science majors of the University of Electro-Communications. The PLA program is created on a personal computer using a text editor and transmitted to the PLA through a serial communication line. Parallel interface circuits between the personal computer and the arithmetic unit to be implemented by the students were also prepared. The arrangements enable them to write and execute Pascal programs to test whether the implementation meets given specifications.
Implementing a function using a programmablelogic array (PLA) can often be very expensive in terms of area. Folding rows and/or columns of a PLA usually leads to a reduction in area. In this paper the problem of faul...
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Implementing a function using a programmablelogic array (PLA) can often be very expensive in terms of area. Folding rows and/or columns of a PLA usually leads to a reduction in area. In this paper the problem of fault detection in folded PLAs is considered. A new fault, the ‘cutpoint’ fault, is described and universal test sets for the detection of this fault are presented. Modifications to existing built-in universally testable design techniques for nonfolded PLAs are presented; the new designs are now applicable to folded PLAs.
programmable logic arrays (PLAs) are characterized by the ability to replace discrete logic components and their equivalent functions in a variety of system designs. With the advent of new technologies and computer so...
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programmable logic arrays (PLAs) are characterized by the ability to replace discrete logic components and their equivalent functions in a variety of system designs. With the advent of new technologies and computer software tools such as Amaze, the exercise of designing with PLAs has been simplified. This paper provides a tutorial overview of various aspects of designing with PLAs, and discusses their uses and basic variations to their structures. A design example involving a single-board computer is presented; the control logic in this design can easily be adapted to other single-board computers.
A recognized model for an all-optical digital computer consists of arrays of optical logic devices interconnected in free space. In order to simplify device requirements and to reduce the complexity of the optics, reg...
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ISBN:
(纸本)0818619864
A recognized model for an all-optical digital computer consists of arrays of optical logic devices interconnected in free space. In order to simplify device requirements and to reduce the complexity of the optics, regular interconnects between logic gates are considered such as crossovers. Problems and solutions related to the computer-aided design of these systems are identified, such as layout, fault avoidance, pipelining, and other considerations. An algorithm for determining settings for an optical programmablelogic array that maintains a strict crossover interconnect at the gate level is described as an example of computer-aided design applied to this model.< >
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