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1989 IEEE CONF ON CUSTOM INTEGRATED CIRCUITS ( CICC 89 )

作者： KATOOZI, M SOMA, M Seattle Silicon Corporation Bellevue WA 98004 307511th Ave. N.E. United States Department of Electrical Engineering University of Washington (FT-10) Seattle WA 98195 United States Microelectronics Laboratory BOEING High Technology Center Bellevue WA United States

A built-in test system that is capable of parallel testing all combinational and sequential arrays on a CMOS chip is presented. The system is based on a recently introduced tristate multiplexing design for programmable and register logic arrays and requires minimal on-chip test storage and silicon area overhead. The test procedure is tailored to the detection of real mask defects in the layout of the array. The system also uses simple and economical data compaction circuit that provides a good fault coverage while not precluding the use of more sophisticated data compactors.

关键词： programmable logic arrays PLA logic testing real mask defects detection combinational arrays CMOS state machines built-in test system parallel testing sequential arrays CMOS chip tristate multiplexing design register logic arrays on-chip test storage test procedure layout data compaction circuit CMOS integrated circuits combinatorial circuits logic arrays logic testing sequential circuits

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Direct Ranking for Voltage Contingency Selection

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IEEE Power Engineering Review 1989年第11期9卷 31-32页

作者： Chen, Yilang Bose, Anjan Department of Electrical Engineering Arizona State University Tempe AZ United States

It is now commonly accepted that for security assessment of a power system, the most efficient and practical strategy is to deal with the problem in two stages. First in contingency selection, those potentially critical contingency cases are ranked by the severity of their impacts on a system. Then in contingency analysis, detailed AC power flows are applied only to the most dangerous cases appearing on top of the ranked list. In the past decade, the problem of ranking outage cases in the order of decreasing severity has attracted a lot of intensive studies, and many efficient and reliable algorithms were developed. But most of these techniques can only be applied to MW limit security problems. On the other hand, voltage problems were also found to be a very important aspect of security assessment. It has become the target of many research projects. Because the MVAR-voltage problem involves a much more complicated model than the MW-angle problem, significant obstacles were experienced in developing ranking algorithms for voltage security monitoring, making it an area where further study is still required. Almost all contingency ranking algorithms employ a scalar performance index to represent a global severity of voltage disturbance after a contingency event. The scalar performance index can be viewed as a weighted distance in voltage space measuring the post contingency voltage profile against specified voltage limits.

关键词： Voltage programmable logic arrays Computational modeling Performance analysis Production systems Costs Piecewise linear approximation Power system security Fast Fourier transforms Power engineering computing

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A 50 MHz uniformly pipelined 64 b floating-point arithmetic processor

A 50 MHz uniformly pipelined 64 b floating-point arithmetic ...

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IEEE International Conference on Solid-State Circuits (ISSCC)

作者： B.J. Benschneider W.J. Bowhill E.M. Cooper M.N. Gavrielov P.E. Gronowski V.K. Maheshwari V. Peng J.D. Pickholtz S. Samudrala Digital Equipment Corporation Hudson MA USA

A description is given of a uniformly pipelined, 50-MHz, 64-b floating-point arithmetic processor implemented in a 1.5- mu m (drawn) CMOS technology which performs single- and double-precision floating-point operations and integer multiplication as defined by a superminicomputer architecture standard. The chip is composed of an interface section and a five-segment execution core. The core insists of a divider, bypassed in all instruction except division, and four fully pipelined stages that are uniformly utilized in the execution of all instructions. The performance is summarized. First pass silicon has been functionally verified at 50 MHz with a set of over one million vectors.< >

关键词： Floating-point arithmetic programmable logic arrays CMOS technology Detectors CMOS process Pipelines Sensor arrays Ducts Signal detection Decoding

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On designing robust testable PLA for path delay faults

On designing robust testable PLA for path delay faults

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Asilomar Conference on Signals, Systems & Computers

作者： B. Gupta R. Rajsuman Computer Science Department Southem Illinois University Carbondale IL USA Department of Computer Engineering & Sciece Case Western Reserve University Cleveland OH USA

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A signal processing perspective to the operational characteristics of perceptron and Hopfield associative memory neural networks

A signal processing perspective to the operational character...

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International Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： M.I. Sezan H. Stark S.-J. Yeh Photographic Research Laboratories Eastman Kodak (Japan) Limited Rochester NY USA Electrical and Computer Engineering Department Illinois Institute of Technology Chicago IL USA

Projection method formulations of the perceptron and Hopfield associative content-addressable memory (ACAM) neural nets are presented. It is shown that the well-known single-layer-perceptron learning algorithm can be formulated using the method of projections onto convex sets (POCS) and that its performance can be improved using this method. The operation of a modified, binary-valued Hopfield ACAM is shown to be equivalent to the method of generalized projections. A direct extension of the binary-valued ACAM to the continuous-valued case lends itself to a POCS formulation.< >

关键词： Signal processing programmable logic arrays Signal processing algorithms Neural networks Hopfield neural networks Convergence Iterative algorithms Performance analysis Associative memory Laboratories

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Adding analog, EPROM and EEPROM modules to CMOS logic technology: how modular?

Adding analog, EPROM and EEPROM modules to CMOS logic techno...

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International Electron Devices Meeting (IEDM)

作者： J. Paterson Semiconductor Process and Design Center Texas Instruments Inc. Dallas TX USA

The issue of modularity (design, process, manufacturing, reliability) in the addition of analog (resistor and capacitor), EPROM (electrically programmable ROM) (12.5-V isolation and cell), and EEPROM (electrically erasable programmable ROM) (18-V isolation, 18-V transistor and cell) modules to core CMOS technologies is discussed. Design modularity permits the design of complex circuits using standard cell logic libraries, process modularity simplifies the task of creating and executing the process flow, manufacturing modularity defines the incremental equipment requirements, and reliability modularity eliminates the need to requalify the core process. Three specific examples are described, including an 18-V EEPROM module for a 1.6- mu m CMOS core for an 8-b microcontroller with EPROM and EEPROM; a 5-V analog module for a 1.0- mu m CMOS core for a 10-b switched-capacitor, analog-to-digital converter (ADC); and a 10-V EEPROM module for a 0.8- mu m CMOS core for a EPROM programmable array logic device.< >

关键词： EPROM CMOS technology CMOS logic circuits Isolation technology Manufacturing processes Read only memory programmable logic arrays Process design Resistors Capacitors

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Correctness verification of VLSI modules supported by a very efficient Boolean prover

Correctness verification of VLSI modules supported by a very...

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IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： P. Lammens L. Claesen H. De Man Inter University Micro Electronics Center Leuven Belgium Kath University Leuven Belgium

A description is given of efficient techniques for checking tautology of a Boolean expression, i.e. whether two Boolean expressions are equivalent, taking into account 'don't care' behavior if necessary. If two Boolean expressions appear to be not equivalent, a test case is generated. The tautology checker has been developed to perform functional and logical verification of combinational modules and is integrated in an environment for formal electrical verification. Its efficiency is based on a delicate and optimized interaction between a carefully chosen set of Boolean rewriting rules and a number of heuristics. A number of test cases show its performance as compared to existing tautology checkers. Figures on industrial PLAs are included.< >

关键词： Very large scale integration Testing programmable logic arrays Silicon compiler Runtime NP-hard problem Computational modeling Boolean algebra Parallel machines

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Easily testable PLA-based finite state machines

Easily testable PLA-based finite state machines

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International Symposium on Fault-Tolerant Computing (FTCS)

作者： S. Devadas H.-K.T. Ma A.R. Newton Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge USA Department of Electrical Engineering and Computer Sciences University of California Berkeley USA

A synthesis procedure, which begins with a state transition graph description of a sequential machine and produces an optimized, easily testable PLA (programmable logic array) based logic implementation, is outlined. A procedure is proposed for constrained state assignment and logic optimization that guarantee testability for all combinationally irredundant crosspoint faults in a PLA-based finite-state machine. No direct access to the flip-flops is required. The test sequences to detect these faults can be obtained using combinational test generation techniques alone. This procedure thus represents an alternative to a scan design methodology. Results are presented to illustrate the efficacy of this procedure. The area/performance penalties in return for easy testability are small.< >

关键词： Automata Circuit testing Circuit faults logic testing programmable logic arrays Sequential analysis Sequential circuits Circuit synthesis Constraint optimization Combinational circuits

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Automatic test program generation for a block oriented VLSI chip design

Automatic test program generation for a block oriented VLSI ...

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European Test Conference

作者： F. Hapke Philips Rhw Hamburg Germany

A system for automatic test program generation is presented that is based on a block-oriented chip design. The testability is verified by a test access checker, test patterns are generated by test pattern generators, and everything is linked together by a test assembler to form a complete chip test. The testing part of the system is known as the computer-aided test (CAT) system, and consists of four programs. The function of the CAT system is to check the testability of the chip design, automatically generate test patterns for individual blocks in the chip design, and combine the test patterns for each individual block into one chip test file.< >

关键词： Automatic testing Very large scale integration Chip scale packaging Test pattern generators System testing Read only memory Sequential analysis programmable logic arrays Reconfigurable logic Flip-flops

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A fault model for PLAs

A fault model for PLAs

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European Test Conference

作者： M.M. Ligthart R.J. Staus Philips Research Laboratories Sunnyvale CA USA

A fault model for programmable logic arrays (PLAs) is discussed that handles four classes of faults: multiple stuck-at faults, multiple bridging faults, multiple crosspoint faults, and faults due to breaks in lines. It is shown that a test that detects all multiple crosspoint faults also detects all multiple stuck-at faults, multiple bridging faults, and any combination of the above. It is also shown that multiple faults form a substantial part of the set of all faults in PLAs. Experiments with test generators show that tests detecting all single testable crosspoint faults also detect all testable stuck-at faults. The experiments also show that the test strategies based on the single-crosspoint fault model cover the greater part of all faults in PLAs.< >

关键词： programmable logic arrays Circuit faults logic testing Fault detection Decoding Test pattern generators Design methodology Built-in self-test logic circuits

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