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检索条件"主题词=Programmable Logic Arrays"

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Testability design for PLA-implemented finite state machine

Testability design for PLA-implemented finite state machine

引用

European Test Conference

作者： M. Renovell S. Rayon Y. Bertrand G. Cambon Laboratoire d'Automatique et de Microélectronique de Montpellier (UA371 CNRS) Université des Sciences et Techniques du Languedoc Montpellier France

Design-for-testability (DFT) techniques are presented for the finite state machine implemented in programmable logic arrays (PLAs). The proposed techniques are developed from physical, electrical and functional points of view. Within the framework of deterministic test, these DFT techniques make the fault under consideration either unlikely to occur, equivalent to other faults, or more easily testable. They allow a significant reduction in fault locations and in fault models. A detailed example illustrates the proposed techniques, highlighting the improvements. It is shown that specific DFT techniques developed for regular structures allow the automatic generation of easily testable functional blocks. For CMOS PLA, the test sequence is reduced in such a way that the automatic generation of self-testable finite-state machines is possible.< >

关键词： Automata programmable logic arrays Circuit faults CMOS technology Design for testability Circuit testing MOS devices Very large scale integration logic circuits Design automation

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A basic CAD-tool for module generation

A basic CAD-tool for module generation

引用

European Conference on Solid-State Circuits (ESSCIRC)

作者： Lars Brange Mats Torkelson Department of Applied Electronics University of Lund Sweden

A basic CAD-tool using a simple grid-like floorplan for placement of cells of varying sizes is presented. It is focused on the generation of physical and behavioural descriptions of data paths but is also suit able for random logic, data path controllers containing PLA's, registers, counters etc. and for analog designs containing OP's, capacitors etc. Two different types of floorplans can be chosen; one resembling the standard cell design approach and one resembling the bit-slice approach. By not assembling the cells with abutment, existing general purpose cell libraries can be used. An easy modifiable interpreting lisp-like language is used as input. Three design examples are discussed, one data path for a decimation filter, one data path for a Viterbi receiver and one multiplier.

关键词： Libraries Routing programmable logic arrays Channel allocation Mesh generation logic design Counting circuits Capacitors Assembly Filters

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An algorithm for a microcontrolled reconfigurable PLA

An algorithm for a microcontrolled reconfigurable PLA

引用

Midwest Symposium on Circuits and Systems (MWSCAS)

作者： T. Ramesh Electrical Engineering Department University Cente Saginaw Valley State University MI USA

The PLA (programmable logic array) has become a major subsystem block in the hardware of many systems. A mapping algorithm and hardware for a reconfigurable PLA (RPLA) interfaced to a general purpose microcontroller are described. The functional reconfigurability is achieved by altering the input literal associated with each product and output terms of the function set. The scheme gives a flexibility in realignment of the functions to be implemented.< >

关键词： programmable logic arrays Reconfigurable logic Hardware Microcontrollers CMOS technology Very large scale integration CMOS logic circuits EPROM Writing Read-write memory

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Selection of analog simulation programs for the VLSI classroom

Selection of analog simulation programs for the VLSI classro...

引用

University/Government/Industry Microelectronics Symposium

作者： A. Hubbard BPA (Technology and Management) Limited Boston MA USA

Various-sized PLA (programmable logic array) circuits were simulated using the programs SPICE2G6, RELAX2, and CAZM. Memory usage and CPU times for transient analysis were plotted versus transistor count. Classroom-related attributes of each simulator are discussed. It is concluded that RELAX2 and CAZM are appropriate simulation tools for the introductory VLSI classroom. SPICE2G6 should be used in the VLSI classroom only when critically considered necessary. In the absence of deliberation, default preference should be given to RELAX2 and CAZM due to their superior performance in computing transient responses of large circuits.< >

关键词： Very large scale integration Circuit simulation programmable logic arrays Computational modeling Analytical models Central Processing Unit Transient analysis Statistics Educational institutions Computer simulation

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Geometry Dependent Bird's Beak Formation for Submicron LOCOS Isolation

Geometry Dependent Bird's Beak Formation for Submicron LOCOS...

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European Conference on Solid-State Device Research (ESSDERC)

作者： P.A. van der Plas N.A.H. Wils R. de Werdt Philips Research Laboratories Eindhoven Netherlands

Bird's beak formation is one of the major problems for LOCOS field isolation. In this paper we demonstrate that the bird's beak length is not a constant, but depends strongly on geometry of the oxidatioin mask for submicron mask dimensions. The bird's beak length can vary up to a factor of 4, dependent on mask geometry. Four independent geometry effects are distinguished and their impact on an IC-process is discussed.

关键词： Geometry Oxidation Etching Tin Bars programmable logic arrays Laboratories Isolation technology Performance evaluation Cause effect analysis

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A strongly fault-secure and strongly code-disjoint realization of combinational circuits

A strongly fault-secure and strongly code-disjoint realizati...

引用

International Symposium on Fault-Tolerant Computing (FTCS)

作者： T. Nanya M. Uchida Tokyo Institute of Technology Tokyo Japan

Strongly fault-secure (SFS) circuits are known to achieve the totally self-checking (TSC) goal of producing a noncodeword as the first erroneous output due to a fault. Strongly code-disjoint (SCD) circuits are known to always map noncodeword inputs to noncodeword outputs, even in the presence of faults, as long as the faults remain undetected. The authors present a general design method for SFS and SCD combinational circuits for the previously proposed fault model that covers the broad classes of likely faults in VLSI. In the design, the input and output of a combinational circuit are encoded in systematic unordered codes whose check part is obtained by adding two extra bits to the check part of any known systematic unordered code. Thanks to the uniform input/output encoding and the SCD property for the proposed combinational circuits, a number of the circuits can be interconnected in cascade to construct a larger SFS combinational circuit if each interface is sufficiently exercised.< >

关键词： Circuit faults Combinational circuits Encoding Integrated circuit interconnections Electrical fault detection Fault detection programmable logic arrays Design methodology Very large scale integration Fault tolerant systems

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Location and identification for single and multiple faults in testable redundant PLAs for yield enhancement

Location and identification for single and multiple faults i...

引用

IEEE International Test Conference

作者： Y.-N. Shen F. Lombardi Department of Computer Science Texas A and M University College Station TX USA

The authors present the basic structure of a testable and repairable programmable logic array (PLA) and the design modifications which are required for a full diagnosis and yield enhancement. The testing process is fully analyzed, and the conditions for diagnosis are presented. It is proved that identification in the presence of multiple (crosspoint, stuck-at, and bridging) faults is possible with high coverage. The criteria which permit diagnosis are based on a hierarchical organization of the testing process; significant improvements over previous redundant structures can be achieved. This results in a compact structure with a homogeneous layout which has been evaluated with respect to area overhead for VLSI implementation. Simulation results for benchmark devices are presented. These suggest that an efficient repair of VLSI PLAs for yield enhancement can be achieved.< >

关键词： Fault diagnosis programmable logic arrays Circuit faults Redundancy Very large scale integration Manufacturing Fault detection logic devices Automatic testing Built-in self-test

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Low-power consumption and low-voltage operation PLA (L/sup 2/-PLA) using 1.2 mu m double poly-silicon CMOS E/sup 2/PROM technology

Low-power consumption and low-voltage operation PLA (L/sup 2...

引用

Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Y. Saeki H. Murakami T. Shigematu K. Shinada M. Takebuchi T. Hibi Y. Suzuki Semiconductor System Engineering Center Toshiba Corporation Kawasaki Japan Toshiba Corp. Kawasaki Japan Microelectronics Center Toshiba Corporation Kawasaki Japan

By using a unique CMOS E/sup 2/PROM technology, a novel field PLA (programmable logic array) has been developed. Owing to very low power consumption and low-voltage operation the PLA (L/sup 2/-PLA) is suitable for most consumer usage. To achieve this performance a soft-write free E/sup 2/PROM, a new low-power sense amplifier and an input transition detector (ITD) are used. L/sup 2/-PLA can operate in a wide range of supply voltage (1.0 V to 6.0 V) and consumes only 8 mA and 1 MHz (5 V supply voltage). Moreover, it has a standby mode in which the current consumption is extremely low (below 1 mu A).< >

关键词： programmable logic arrays CMOS technology Low voltage Nonvolatile memory logic circuits Power engineering and energy Systems engineering and theory Microelectronics CMOS logic circuits Energy consumption

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Manual rescheduling and incremental repair of register-level datapaths

Manual rescheduling and incremental repair of register-level...

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IEEE International Conference on Computer-Aided Design

作者： D.W. Knapp Computer Science Department University of Illinois Urbana-Champaign Urbana IL USA

A description is given of new capabilities of the RLEXT register level exploration tool. RLEXT is an interactive tool that takes a datapath design and allows a user to modify it freely, using transformations that do not themselves preserve correctness. By maintaining a representation of the desired behavior and timing as well as structure, RLEXT is able to 'repair' the design when the user creases modifying, so that the ability of the design to express the specified behavior is once again guaranteed. A description is also given of RLEXT's support for manual changes of schedule in the presence of an existing data-path structure. Such schedule changes invalidate the structure, but the structure is incrementally repaired rather than just thrown out. The author knows of no other high-level synthesis tool that supports this kind of functionality.< >

关键词： High level synthesis Timing Topology Algorithm design and analysis Computer science Hardware design languages Synthesizers Engines programmable logic arrays Software performance

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A built-in self-test PLA design with full fault coverage

A built-in self-test PLA design with full fault coverage

引用

Midwest Symposium on Circuits and Systems (MWSCAS)

作者： T.N. Rajashekhara A.S. Nale Department of Electrical Engineering State University of New York Binghamton Binghamton NY USA

A built-in self-test (BIST) PLA (programmable logic array) design using a new technique for on-chip storage and retrieval of the compressed signature of a fault-free PLA is proposed. The design uses function-independent test input sequences, and provides function-independent test responses. Additional features of the proposed BIST PLA design are: (1) simplified implementation of test evaluator, (2) reduced test length (2n/sub i/n/sub p/ test inputs for a PLA with n/sub i/ inputs and n/sub p/ product lines), (3) full fault coverage in the naked PLA, (4) crosspoint fault locatability, and (5) only three extra pinouts. The proposed input decoder augmentation will not result in any performance degradation. With these features, the proposed design is more efficient than other BIST PLA designs reported in the literature.< >

关键词： Built-in self-test programmable logic arrays Circuit testing Circuit faults Automatic testing Degradation logic functions Decoding logic arrays Combinational circuits

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