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检索条件"主题词=Programmable Logic Arrays"

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Horizontal Partitioning of PLA-based Finite State Machines

Horizontal Partitioning of PLA-based Finite State Machines

引用

Design Automation Conference

作者： P.G. Paulin I.N.P.G/CSI Grenoble France BNR Limited Ottawa Canada

We present a new form of partitioning of PLA-based FSMs that combines the advantages of traditional vertical PLA partitioning (i.e. via inputs and/or outputs) and counter embedding which consists of replacing the FSM state memories by a counter. Like the former, horizontal partitioning allows the reduction of the number of input and/or output columns in the PLAs resulting from the partition. Furthermore, the technique also reduces the total number of product terms, as in counter embedding techniques. This reduction is due to a decomposition of state transitions into two classes that are realized by two sets of logic. In this case however, a second PLA-based FSM is used in place of the counter. This results in area reductions of 30% to 60% (with respect to regular two-level logic minimization) for the benchmark examples presented.

关键词： Automata programmable logic arrays Counting circuits Partitioning algorithms Permission Minimization logic testing Control system synthesis Benchmark testing logic arrays

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Optimal layout via Boolean satisfiability

Optimal layout via Boolean satisfiability

引用

IEEE International Conference on Computer-Aided Design

作者： S. Devadas Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge USA

The author transforms various NP-complete problems in layout, namely, two- and multilayer dogleg channel routing, two-way partitioning, one-dimensional and two-dimensional placement, into Boolean satisfiability problems. The transformations are efficient in that the number of inputs to the Boolean function, for which he has to find a satisfying assignment, only grows linearly or quasilinearly with the layout problem size. These transformations also produce a minimal-size Boolean function in order to speed up satisfiability check performance.< >

关键词： Paper technology Boolean functions Fires Costs programmable logic arrays Large-scale systems

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Circuit placement in arbitrarily-shaped region using self-organization

Circuit placement in arbitrarily-shaped region using self-or...

引用

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Jung-Soo Kim Chong-Min Kyung Department of Electrical Engineering Korea Advanced Institute of Science and Technology Seoul South Korea

Effective circuit placement in rectilinear or arbitrarily shaped region is achieved by preplacement of some macro cells. The method is based on the self-organization process proposed by T. Kohonen (Self Organization and Associati Memory, Springer-Verlag, 2nd ed., 1988). The self-organization process is a learning algorithm for neural networks that adjusts the weights of synapses (links) connecting nodes and inputs so that nodes connected closely topologically are sensitive to inputs having similar properties. The authors obtained a good placement result in an arbitrarily shaped region when the cells of the circuit and their positions (x- and y-coordinates) have a one-to-one correspondence with the nodes and the weighted pairs of synapses connected to the nodes, respectively. This method can be easily extended to circuit placement over a nonplanar surface.< >

关键词： Neural networks Network topology Circuit topology Pain Integrated circuit interconnections programmable logic arrays Read only memory Two dimensional displays

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State assignment for multilevel logic using dynamic literal estimation

State assignment for multilevel logic using dynamic literal ...

引用

IEEE International Conference on Computer-Aided Design

作者： M. Bolotski D. Camporese R. Barman Department of Electrical Engineering University of British Columbia Vancouver BC Canada

The problem of assigning a representation for the states in a finite-state machine (FSM) so as to minimize the area required for implementation using multilevel logic is considered. The problem is reduced to one of minimizing the literal count in the combinational logic part of the FSM. Heuristics are used to guide the selection of candidate state assignments, and a fast literal estimator is used to choose the best assignment from among the candidates. This approach is compared to the mustang program and is found to produce, on average, smaller literal counts than mustang.< >

关键词： State estimation programmable logic arrays Libraries Encoding Automata Circuit synthesis Equations Minimization Computer networks Costs

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An approach for the yield enhancement of programmable gate arrays

An approach for the yield enhancement of programmable gate a...

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IEEE International Conference on Computer-Aided Design

作者： V. Kumar A. Dahbura F. Fischer P. Juola AT and T Bell Laboratories Holmdel NJ USA AT and T Bell Laboratories Murray Hill NJ USA AT and T Bell Laboratories Allentown PA USA AT&T Bell Labaratories Holmdel NJ USA

programmable gate arrays (PGAs) offer a convenient means of prototyping complex logic. An approach is presented for enhancing the yield of PGAs through defect tolerance. This serves two purposes: to make the product economical, as well as to help reduce the turnaround time. The approach is based on using programmable interconnect to test the logic in the PGA and to use adaptive customization to avoid the defective portions. The ideas are illustrated through the use of a novel PGA architecture. Heuristics for adaptive customization of the PGAs are given and their effectiveness is studied through yield analysis. The results of the study for a sample circuit are included.< >

关键词： programmable logic arrays Electronics packaging logic programming Integrated circuit interconnections logic gates Prototypes Fuses logic circuits logic devices logic testing

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Automatic synthesis of VLSI control paths for high level specifications

Automatic synthesis of VLSI control paths for high level spe...

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IEEE Southeastcon

作者： S.-T. Su R.Z. Makki S.-S. Chen S. Bou-Ghazale North Carolina State University Charlotte NC USA

A tool is presented for designing finite-state machines. The tool allows for several synthesis options which include: one-shot encoding; programmable logic arrays; and decoding and minimization. A common high-level description capability is provided for all three synthesis options. The proposed tool, called SSC (structured system control), is applied to the design of a control path for a neural net model. The advantages and disadvantages of each synthesis option are discussed.< >

关键词： Very large scale integration Automatic control Circuit synthesis programmable logic arrays Circuit testing Control system synthesis Decoding Minimization methods logic circuits Flip-flops

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A programmable high performance processor using the residue number system and CMOS VLSI technology

A programmable high performance processor using the residue ...

引用

IEEE National Conference on Aerospace and Electronics (NAECON)

作者： R.A. Hohne R. Siferd Department of Electrical Engineering Wright State University Dayton OH USA

The authors describe the general architecture of RNS (residue number system) processors, the VLSI implementation of the associated hardware, and finally, an RNS processor designed by the authors. The 2- mu m CMOS implementation of the processor performs a 16*16 b (signed or unsigned) multiply-accumulate with 32-b accuracy at clock speeds greater than 20-MHz. It is noted that the advantages of the RNS over traditional binary computers is mainly speed. This advantage comes at a cost of larger hardware size, with a reduction in design complexity and design time due to the use of programmable logic arrays in a VLSI environment. Signed or unsigned operations take the same amount of time, use the same basic hardware, and have roughly equal delays for addition, subtraction, and multiplication. The disadvantage of this approach is that it is difficult or impossible to perform magnitude comparisons, bitwise operations, or division while the number is in RNS format.< >

关键词： Hardware programmable logic arrays Very large scale integration Process design CMOS process Clocks Costs logic design Added delay Delay effects

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Using PROLOG for digital circuits simulation

Using PROLOG for digital circuits simulation

引用

Mediterranean Electrotechnical Conference (MELECON)

作者： T. Welzer I. Rozman J. Gyorkos Faculty of Technical Sciences University of Maribor Maribor Yugoslavia

The use of PROLOG for digital circuit simulation in the education process is discussed. It is noted that the curriculum of the University of Maribor gives electrical engineering students some basic knowledge of computer techniques and FORTRAN or Pascal. On this basis, PROLOG can be presented to the students in order to acquaint them with some fundamentals of this fifth-generation language. The students who have acquired basic knowledge of PROLOG are able to define digital circuits specification programs as well as other simple PROLOG rules. The experience that students gain makes them capable of understanding similar models of conventional engineering as well as the basic working of expert systems.< >

关键词： Digital circuits Circuit simulation logic circuits programmable logic arrays Digital systems Computer languages Computational modeling Electrical engineering Expert systems logic gates

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Computations over finite monoids and their test complexity

Computations over finite monoids and their test complexity

引用

International Symposium on Fault-Tolerant Computing (FTCS)

作者： B. Becker U. Sparmann Fachbereich 10 Universität des Saarlandes Saarbruecken Germany

The authors consider the test pattern generation problem for circuits than compute expressions over some algebraic structure. The relation between the algebraic properties of this structure and its test complexity is analyzed. This relation is looked at in detail for the family of all finite monoids. The test complexity of a monoid with respect to a problem is measured by the number of tests needed to check the best testable circuit (in a certain computational model) that will solve the problem. Two important computations over finite monoids, namely, expression evaluation and parallel prefix computation, are considered. In both cases it can be shown that the set of all finite monoids partitions into exactly three classes with constant, logarithmic, and linear test complexity, respectively. These classes are characterized using algebraic properties. For each class, circuits are provided with optimal test sets and efficient methods, which decide the membership problem for a given finite monoid M.< >

关键词： Circuit testing Concurrent computing Adders Very large scale integration logic arrays Computational modeling Test pattern generators Marine vehicles Combinational circuits programmable logic arrays

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Design assurance in a university setting

Design assurance in a university setting

引用

IEEE International Test Conference

作者： K. Rose Center for Integrated Electronics Rensselaer Polytechnic Institute Troy NY USA

It is argued that VLSI design assurance in a university setting requires developing an environment in which a multiplicity of reliable designs can be produced by inexperienced designers at minimal costs. Two issues in design verification and testing are examined: the first relates to design for testability; the second is the practical verification of designs once they are implemented in silicon. It is concluded that as problems associated with design assurance are solved, the results should be of value to a broader community and especially to ASIC (application-specific integrated circuit) designers.< >

关键词： Design automation Very large scale integration Process design Application specific integrated circuits Silicon Electronic equipment testing programmable logic arrays Assembly systems Routing Standards development

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