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检索条件"主题词=Programmable Logic Arrays"

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State Assignment Using a New Embedding Method Based on an Intersecting Cube Theory

State Assignment Using a New Embedding Method Based on an In...

引用

Design Automation Conference

作者： G. Saucier C. Duff F. Poirot I.N.P.G/CSI Grenoble France Route des Dolines Sophia Antipolis VLSI Technology Inc. La Valbonne France

The controller state assignment methodology proposed here features two improvements over existing methods. First, a larger set of predictive minimizations in the control flowgraph is performed. Secondly, the embedding phase uses a new theory of intersecting cubes in the Boolean lattice. Practical results using the VLSI Technology logic-Synthesizer on both PLA and multi-level logic demonstrate the effectiveness of the approach.

关键词： Equations Hypercubes Lattices Minimization Very large scale integration programmable logic arrays Binary codes Permission Synthesizers Flowcharts

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Digital design using erasable PLDs

Digital design using erasable PLDs

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IEEE Southeastcon

作者： P.K. Lala Department of Electrical Engineering North Carolina Agriculture and Technical State University Greensboro NC USA

The author considers the impact of the newer generations of PLDs (programmable logic devices) on digital design. Particular attention is given to the features of the AND-OR-structured PLDs. It is concluded that the variety of PLDs on the market has given a novel perspective to digital system design. Gate capacities are increasing continuously and reprogrammable architectures are being proposed. Coupled with the dramatic improvements in bipolar and CMOS processes, PLDs now offer greater density, higher speed, and lower power consumption.< >

关键词： programmable logic arrays logic devices Fuses logic arrays logic testing Security Mirrors Chromium Ducts State feedback

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Algorithm design for a 30-bit integrated logarithmic processor

Algorithm design for a 30-bit integrated logarithmic process...

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Computer Arithmetic (ARITH)

作者： D.M. Lewis L.K. Yu Department of Electrical Engineering University of Toronto Canada

A description is given of the architecture of an integrated processor that is capable of performing addition and subtraction of 30-b numbers with 20 fractional bits in the logarithmic number system. Previous techniques would require 70 Mb of ROM to implement this processor, which is not feasible for a single-chip implementation. The techniques presented here use a factor of 275 less memory. The key to this is the use of a linear approximation of the nonlinear functions stored in the lookup tables. The functions involved are highly nonlinear in some regions, so variable size regions are used for the approximation. The use of linear approximation alone would still require over 565 kb of ROM. Further compression is obtained by using linear approximation with differential coding of each table. The compression is chosen to minimize ROM size and obtains a further reduction of 55%. A total of 260 kb of ROM is required to implement the processor.< >

关键词： Algorithm design and analysis Linear approximation Read only memory Table lookup Space technology programmable logic arrays Hardware Arithmetic Merging

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A 76 MHz programmable logic sequencer

A 76 MHz programmable logic sequencer

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IEEE International Conference on Solid-State Circuits (ISSCC)

作者： C. Sung P. Sasaki R. Leung Y.M. Chu K. Le G. Conner R. Lane J.L. de Jong R. Cline Application Specific Products Division Signetics Company Sunnyvale CA USA Advanced Technology Development Signetics Company Sunnyvale CA USA

The authors describe a BiCMOS programmable logic sequencer which provides reduced power, has functional density and flexibility similar to that of CMOS, and maintains speed as high as that of bipolar devices. The device is organized as 16 inputs, 48 product terms, and 8 registered outputs. Both logic AND and OR arrays are designed for user-programmability, enabling any chosen product term to be shared as a common sum-of-products by all of the outputs without resorting to a large number of product terms. A separate BiCMOS programming path test chip, compatible with this device, was manufactured simultaneously and evaluated separately. The equivalent gate count for this device is approximately 1000 gates. A maximum operating frequency of 76 Mhz, with 6-ns clock to output delay and 7-ns input setup time at a power dissipation of 370 mW, has been achieved. The process used to fabricate this device is a merged bipolar and CMOS technology featuring 1.9- mu m L/sub eff/ and 1.2- mu m*3- mu m emitter, three-layer metal and single-layer polycide for interconnections, TiW fuses, PtSi Schottky diodes, and polysilicon resistors.< >

关键词： programmable logic arrays programmable logic devices CMOS logic circuits logic devices BiCMOS integrated circuits logic arrays CMOS technology logic design logic programming Testing

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The integration of logic synthesis and high-level synthesis

The integration of logic synthesis and high-level synthesis

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： R. Camposano L.H. Trevillyan IBM Research Division Thomas J. Watson Research Center Yorktown Heights NY USA

The relationship between high-level synthesis and logic synthesis is investigated and the factors that influence the interface between them are discussed. It is contended that there must be close integration of the two synthesis processes if automatic synthesis of efficient designs from behavioral specifications is to be useful. Results from several experiments that show some basic tradeoffs are given.< >

关键词： High level synthesis logic design Libraries Job design Design optimization Boolean functions programmable logic arrays Equations Turning Manufacturing

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Improving response time of programmable logic controllers by use of a Boolean coprocessor

Improving response time of programmable logic controllers by...

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CompEuro

作者： J. Donandt AEG Research Institute Berlin Berlin Germany

ISBN: (纸本)0818619406

programmable-logic controllers (PLCs) are widely used to control technical processes in the industrial environment. In the requirements for next-generation PLCs, their fast response to events from the controlled processes plays a central role. The author shows that the response time of a low-cost PLC can be shortened by at least a factor of ten by using a special Boolean coprocessor in conjunction with the PLC (micro-) processor. The speedup is achieved by two means: (1) an architecture of the Boolean coprocessor designed for very fast execution of instructions on bit data, and (2) parallel execution of bit- and word-instruction streams with an efficient synchronization mechanism between them. The Boolean coprocessor's design is completed at the register transfer level. Simulation at the register transfer level and a gate-level simulation of the critical data path indicate an instruction-cycle time of less than 0.3 mu s. The VLSI realization of the design requires a gate array of 4000 gates with a 2-kb fast on-chip RAM.< >

关键词： Delay Boolean functions programmable logic arrays programmable logic devices programmable control Coprocessors Process control Microprocessors Industrial control Centralized control

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Minimization of multiple-valued input multi-output mixed-radix exclusive sums of products for incompletely specified Boolean functions

Minimization of multiple-valued input multi-output mixed-rad...

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International Symposium on Multiple-Valued logic

作者： M. Perkowski M. Helliwell P. Wu Department of Electrical Engineering Portland State University Portland OR USA

The concept of a mixed-radix multiple-valued input exclusive sum of products (MRESP) is presented, and some possible circuit realizations for the concept are discussed. The algorithm starts from a Boolean function and generates an approximate MRESP form and the appropriate multioutput circuit. Such circuits can have smaller complexity than the EXOR forms with mixed polarity, the PLAs with decoders, and the networks with two-variable function generators. They are also easily testable.< >

关键词： Minimization Circuit testing Boolean functions programmable logic arrays Decoding logic design logic circuits logic testing Signal generators Very large scale integration

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Practical built-in test of CMOS state machines with realistic faults

Practical built-in test of CMOS state machines with realisti...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： M. Katoozi M. Soma Seattle Silicon Corporation Bellevue WA USA Department of Electrical Engineering University of Washington Seattle WA USA

A design-for-test scheme is presented that is capable of testing programmable and register logic arrays with the same low-cost test hardware. This scheme detects real faults resulting from mask defects in the circuit, is practical to implement, and can be adopted as a built-in-test system using readily available modules in application-specific integrated circuits.< >

关键词： Built-in self-test logic testing Circuit testing programmable logic arrays Design for testability Registers CMOS logic circuits logic design Hardware Electrical fault detection

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On Yield Consideration for the Design of Redundant programmable logic arrays

On Yield Consideration for the Design of Redundant Programma...

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Design Automation Conference

作者： Chin-Long Wey Department of Electrical Engineering Michigan State University East Lansing MI USA

This paper presents the design of a programmable logic array with redundancy. The design allows for the repair of a defective chip by including the redundancy circuits to a conventional PLA. When the redundancy technique is implemented into the VLSI or WSI chip design, the increased cost is proportional to the increased chip silicon area. Indeed, the additional spare lines may increase the silicon area and propagation delay. However, if the provided redundancy can be efficiently utilized to repair the defective chip, then the additional spare lines may increase rather decrease the chip yields. The objective of the present paper is to analyze the possibility of yield enhancement rhrough redundant design.

关键词： programmable logic arrays logic design Redundancy Circuit faults Very large scale integration Manufacturing Permission logic testing Silicon Built-in self-test

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BIST-PLA: A Built-In Self-Test Design of Large programmable logic arrays

BIST-PLA: A Built-In Self-Test Design of Large Programmable ...

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Design Automation Conference

作者： Chun-Yeh Liu K.K. Saluja J.S. Upadhyaya Department of Electrical and Computer Engineering University of Wisconsin Madison Madison WI USA Department of Electrical and Computer Engineering State University of New York University at Buffalo Buffalo NY USA

A new method for designing a Built-In Self-Test programmable logic Array (BIST-PLA) is presented. In the proposed design, the Test Pattern Generator and the Response Evaluator circuits are very simple. The design requires a rearrangement of the AND (OR) planes on the basis of number of crosspoints in the product (output) lines in the PLA. The BIST-PLA proposed in this paper is capable of detecting all single stuck-at and crosspoint faults and almost all multiple faults, thus offering fault coverage higher than any of the known BIST designs of PLAs. A program has been written which generates a BIST-PLA. The program was used to study 22 large PLAs from the list of 56 PLAs given in [18]. It was found that the silicon area overhead for almost all these PLAs was lower than those using methods reported in literature [10] [11] [12] [13] [14] [15] [16] [17]. Furthermore, the delay performance degradation was found to be within acceptable limits. The program was developed in the unix environment (4.3beta BSD UNIX) and is integratable with the existing design automation tools.

关键词： programmable logic arrays Built-in self-test logic design Circuit faults Design methodology Test pattern generators Electrical fault detection Fault detection Silicon Delay

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