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IEEE DESIGN & TEST OF COMPUTERS 1988年第4期5卷 14-28页

作者： ZHU, XA BREUER, MA UNIV SO CALIF DEPT ELECT ENGNLOS ANGELESCA 90089 UNIV TEXAS DEPT ELECT & COMP ENGNAUSTINTX 78712

A framework is presented for evaluating methods of testing programmable logic arrays (PLAs), and the attributes of 25 test design methodologies are tabulated. PLA testing problems are first examined, and several test-generation algorithms are briefly described. Techniques for designing testable designs are examined, namely, special coding, parity checking, signature analysis, divide and conquer, and fully testable PLAs. The attributes that make a good testable design are then discussed. They fall into four categories: (1) testability characteristics; (2) effect on original design; (3) requirements of the application environment; and (4) design costs, i.e. how difficult it is to implement the technique.

关键词： programmable logic arrays logic testing Hardware logic design Design methodology logic arrays System testing Time division multiplexing Design optimization Area measurement

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2 NP-HARD INTERCHANGEABLE TERMINAL PROBLEMS

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1988年第4期7卷 467-472页

作者： SAHNI, S WU, SY Computer Science Department University of Minnesota Minneapolis MN USA

Two subproblems that arise when routing channels with interchangeable terminals are shown to be NP-hard. These problems are: (1) determining whether there is a net-to-terminal assignment that results in an acyclic vertical and constraint graph and (2) for instances with acyclic vertical constraint graphs, obtaining net-to-terminal assignments for which the length of the longest path in the vertical constraint graph is minimum.< >

关键词： Routing programmable logic arrays programmable logic devices Computer science NP-complete problem Design automation

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HEURISTIC ALGORITHM FOR THE MINIMIZATION OF GENERALIZED BOOLEAN FUNCTIONS

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IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES 1988年第2期135卷 108-116页

作者： CARUSO, G Dipartimento di Ingegneria Elettrica Università di Palermo Palermo Italy

Generalised Boolean functions are useful in the design of programmable logic arrays. In this paper a heuristic algorithm suitable to minimise such functions is presented. The algorithm generates an irredundant cover by using a local approach to select generalised prime implicants. A benefit of such a method is that the preliminary generation of the set of all the generalised prime implicants is not required. Experimental results are presented, showing a favourable comparison with an already established minimisation algorithm as far as computing speed is concerned.

关键词： logic circuits logic and switching circuits minimisation Optimisation techniques cellular arrays Formal logic programmable logic arrays generalised Boolean functions Boolean functions heuristic algorithm

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THE 3D KALEIDOSCOPE

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IEEE COMPUTER GRAPHICS AND APPLICATIONS 1988年第5期8卷 9-14页

作者： BLINN, JF Caltech Pasadena USA

The author presents a method for constructing platonic solids that takes advantage of their symmetry. This works well with a coordinate transform system, since symmetry is based on coordinate transformations. He treats the cube and other related shapes, using a seed-triangle element that can be rotated and reflected to generate the shape. He shows that the seed triangle can be replaced with any shape whatever, and all the replications will generate a result that also shares the symmetry of the cube. By making the seed shape rotate and move about in some random way, a changing shape that generates the 3-D kaleidoscope patterns of the title can be animated. The tetrahedron is also treated.< >

关键词： Shape Reflection Solids Mirrors Switches programmable logic arrays Joining processes

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A 50-NS CMOS 256K EEPROM

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1988年第5期23卷 1164-1170页

作者： TING, TKJ CHANG, T LIN, T JENQ, CS NAIFF, KLC Microchip Technology Inc. Chandler AZ USA

A 32 K*8 EEPROM (electrically erasable programmable read-only memory), which operates with a single 5-V power supply and achieves 100 K cycle endurance, 50-ns typical read access time, and 1-ms page programming time, equivalent to 16 mu s/byte, was designed. A double-poly, double-metal, n-well CMOS process with 1.25- mu m minimum feature size was developed to manufacture the device. The required and optional extended JEDEC standards for software data protection and chip clear are implemented along with parity check, toggle bit, page-load timer, and data-protection status bit. A modified Hamming code, which uses four parity bits per byte, was implemented to detect and correct single-bit errors.< >

关键词： EPROM Latches logic programming Signal generators programmable logic arrays Iron Parity check codes Error correction Timing Clocks

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A KNOWLEDGE-BASED SYSTEM FOR SELECTING TEST METHODOLOGIES

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IEEE DESIGN & TEST OF COMPUTERS 1988年第5期5卷 41-59页

作者： ZHU, XA BREUER, MA UNIV SO CALIF DEPT ELECT ENGNLOS ANGELESCA 90089 UNIV SO CALIF COMP SCILOS ANGELESCA 90089 UNIV TEXAS DEPT ELECT & COMP ENGNAUSTINTX 78712

A prototype knowledge-based system that helps select test methodologies for a particular type of logic structure is described. The system, called TDES, (testable design expert system), is a subsystem of Adam, an advanced design automation system. The system is being used to test programmable logic arrays, but its architecture is applicable to other types of structures such as RAMs, ROMs, and other combinational logic. It uses a divide-and-conquer (partitioning) strategy and works interactively with a user as an intelligent consultant and assistant.

关键词： Knowledge based systems System testing Circuit testing logic testing Time division multiplexing Kernel Automatic testing Design automation programmable logic arrays Very large scale integration

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A NEW APPROACH TO THE DESIGN OF BUILT-IN SELF-TESTING PLAS FOR HIGH FAULT COVERAGE

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1988年第1期7卷 60-67页

作者： UPADHYAYA, SJ SALUJA, KK UNIV WISCONSIN DEPT ELECT & COMP ENGNMADISONWI 53706

Four critical requirements are identified for the built-in self-testing of programmable logic arrays (BIST PLAs): the test set to test the PLA as well as the output response must be independent of the function of the PLA; the test pattern generator (TPG) and the response evaluator circuits must be simple to keep the extra logic overhead to a minimum; the fault coverage of the PLA must be within acceptable limits; and the speed of the test application must be high. A design that meets all of these goals is proposed. The approach is based on counting crosspoints, as opposed to the conventional parity technique. The TPG and RE circuits are simple and consist of shift registers and counters. The design requires a reorganization of the columns of the PLA on the basis of the number of crosspoints. This design provides extremely high fault coverage: the coverage for multiple faults is higher than that of any BIST design known to the authors, and the single-fault coverage is 100%. The design is simple and can easily be incorporated into existing computer-aided design systems.< >

关键词： Built-in self-test programmable logic arrays Circuit testing logic testing Automatic testing Circuit faults logic circuits Fault diagnosis Test pattern generators Shift registers

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USER-programmable GATE arrays

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IEEE SPECTRUM 1988年第13期25卷 32-35页

作者： FREEMAN, R Xilinx Inc.

A very flexible gate array that speeds the job of designing, updating, or varying the logic circuitry that turns standard microprocessor and memory ICs into computers and peripheral equipment is examined. The gates on this kind of IC are interconnected under software control, and downloaded into local memory cells from a program written by the user, which can alter it almost at will. The array is manufactured with a grid of interconnections consisting of metal segments and programmable switching points. The user's program defines which switching points are on and which are off, and in this way groups and interconnects the gates into useful functions. On conventional gate-array ICs, the interconnections are made once and for all by the manufacturer using photolithographic masks. Various types of arrays and methods for programming them are described. The approach to designing them is discussed, highlighting differences from the process for factory-configured gate arrays. Some example applications are presented

关键词： Integrated circuit interconnections logic arrays programmable logic arrays Computer peripherals Manufacturing Job design logic design logic circuits Flexible printed circuits Microprocessors

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AN ALGORITHM FOR IDENTIFYING AND SELECTING THE PRIME IMPLICANTS OF A MULTIPLE-OUTPUT BOOLEAN FUNCTION

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1988年第11期7卷 1215-1218页

作者： PERKINS, SR RHYNE, T MICROELECTR & COMP TECHNOL CORP AUSTIN TX 78759 USA UNIV TEXAS DEPT ELECT & COMP ENGN AUSTIN TX 78712 USA

A multiple-output Boolean minimization procedure is presented that generates a minimum cover with computational efficiency by extending the directed search algorithm to the multiple-output case. This procedure is applicable to manual execution as well as to automated execution, and to both conventional two-level gating structures and programmable logic arrays (PLAs).< >

关键词： Minimization methods programmable logic arrays Boolean functions Algorithm design and analysis Merging Computer science Lakes Microelectronics Manuals Design automation

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STRONGLY FAULT SECURE PLAS AND TOTALLY SELF-CHECKING CHECKERS

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IEEE TRANSACTIONS ON COMPUTERS 1988年第7期37卷 863-867页

作者： MIN, YH LI, JT Inst. of Comput. Technol. Acad. Sinica Beijing China

A general approach is presented to the design of totally self-checking (TSC) programmable logic arrays (PLAs). A strongly fault secure (SFS) implementation is suggested for the functional PLA, which is shown to be SFS whenever the output is encoded by two-rail code. K-unit TSC checker (TSCC) element are defined to construct TSC checkers. The TSCC is very appropriate for the companion of the SLF PLA since a given input codeword set is sufficient for testing the TSCC. The minimum number of tests needed for a type-m two-rail code K -unit TSCC is 12m. This is a generalization of the fact that four test patterns are sufficient for testing an XOB parity checker tree. As an application, a novel design of a TSC comparator with an arbitrary number of inputs is presented

关键词： Cellular arrays Comparators Circuits logic Testing Strongly Fault Secure PL As Totally Self Checking Checkers programmable logic arrays Two Rail Code XOB Parity Checker Tree Comparator programmable logic arrays Circuit Faults Circuit Testing Built In Self Test Digital Filters Electrons logic arrays Out Of Order Circuit Simulation Speech Processing

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