Reports a new concept for transverse folding of programmable logic arrays (PLAs). With the new definitions for the compatibility and foldability of rows (columns) of a column-folded (row-folded) PLA, the transverse co...
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Reports a new concept for transverse folding of programmable logic arrays (PLAs). With the new definitions for the compatibility and foldability of rows (columns) of a column-folded (row-folded) PLA, the transverse compatibility-cum-foldability matrix (TCFM) is plotted. From the TCFM, a transverse folding matrix (TFM) is found, from which the row (column) folding pairs and the resulting ordering of rows and columns are obtained
A FASTBUS master module, 68K20FPI (68020 FASTBUS Processor Interface), which has the Motorola MC68020 32-bit microprocessor unit (MPU) and the MC68881 floating point coprocessor (FPCP), is presented. The 68K20FPI is i...
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A FASTBUS master module, 68K20FPI (68020 FASTBUS Processor Interface), which has the Motorola MC68020 32-bit microprocessor unit (MPU) and the MC68881 floating point coprocessor (FPCP), is presented. The 68K20FPI is intended to be used for a second-level trigger processor in a multiprocessor environment. It has a local-memory sunboard of 1-Mb static RAMs and a 512-kb ROM port, which are accessed from both the CPU and FASTBUS side. The SCSI (Small Computer Systems Interface) is adopted as a disk interface and also as a high-speed ( approximately 4-Mb/s) interface to other computers. The Ethernet interface is used for a communication line between the 68K20FPIs and a host computer. Two RS232C interfaces are used as terminal and host communication ports. A NIM level input and output are used for trigger purposes.< >
The behavior of gas emissions generated from plastic materials with high resistance to heat was studied by gas chromatography and gas chromatograph-mass spectrometry. The results show the effects of these gas emission...
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The behavior of gas emissions generated from plastic materials with high resistance to heat was studied by gas chromatography and gas chromatograph-mass spectrometry. The results show the effects of these gas emissions on contact reliability and suggest appropriate means for reducing such emissions. Also, as a result of examination of the organic carbon on the contact surfaces by electron spectroscopy for chemical analysis, it was found that gas emissions generated from high-heat-resistant plastics do not form any organic membranes on the contact surface.< >
When designing fault-tolerant systems including programmable logic arrays (PLAs), the various aspects of these circuits concerning fault diagnosis have to be taken into account. The peculiarity of these aspects, rangi...
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When designing fault-tolerant systems including programmable logic arrays (PLAs), the various aspects of these circuits concerning fault diagnosis have to be taken into account. The peculiarity of these aspects, ranging from fault models to test generation algorithms and to self-checking structures, is due to the regularity of PLAs. The fault model generally accepted for PLAs is the crosspoint defect; it is employed by dedicated test generation algorithms, based on the fact that PLAs implement a two-level combinational function. The problem of accessing inputs and outputs of the PLA can be alleviated by augmenting the PLA itself so as to simplify the test vectors to be applied, making them function independent in the limit. A further step consists in the addition of the circuitry required to generate test vectors and to evaluate the answer, thus obtaining a built-in self-test (BIST) architecture. Finally, high reliability can be achieved with PLAs featuring concurrent error detection.
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OZGUNER, FDepartment of Electrical Engineering
The Ohio State University Abstract Authors References Cited By Keywords Metrics Similar Download Citation Email Print Request Permissions
A method for the deductive fault simulation of faults in inverter-free circuits is presented. It is shown that in an inverter-free circuit, fault lists on lines with complementary logic values are disjoint, and fault ...
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A method for the deductive fault simulation of faults in inverter-free circuits is presented. It is shown that in an inverter-free circuit, fault lists on lines with complementary logic values are disjoint, and fault list calculations can be done by performing fewer set operations compared to conventional gate level deductive simulation. Applications of the method to programmable logic arrays (PLA"s) and deductive fault simulation of PLA faults are discussed.
A brief overview of a development system, the Altera PLDS2 (programmablelogic development system), is presented. The use of the PLDS2 in a laboratory course for digital logic design is reported to have made it possib...
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A brief overview of a development system, the Altera PLDS2 (programmablelogic development system), is presented. The use of the PLDS2 in a laboratory course for digital logic design is reported to have made it possible for students to choose between TTL and CMOS-based EPLDs on the basis of cost effectiveness. The Altera PLDS2 is a complete hardware and software development system that enables the circuit designer (students) to develop an optimized code for programming the 'target' Altera EPLDs. The system allows various design input techniques for different logic design tasks. These inputs include schematic capture, netlist entry, Boolean-equations entry, and state-machine entry. Students are not restricted to just one entry method but may 'mix and match' methods to best meet the needs of the overall logic design.< >
The authors present a macro cell generator for flexible multilevel nMOS NOR arrays. A two-dimensional column and row folding algorithm optimizes area usage and cell shape. The accurate control of the shape is realized...
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The authors present a macro cell generator for flexible multilevel nMOS NOR arrays. A two-dimensional column and row folding algorithm optimizes area usage and cell shape. The accurate control of the shape is realized in combination with top down floorplanning. Compared to programmable logic arrays, the cell generator allows for multilevel logic decomposition, and generates denser and more flexible layouts. The folding algorithm uses an elegant hierarchical divide and conquer technique, and produces results that are 59% smaller than those of a simulated annealing approach.< >
A method for the state assignment of finite sequential machines is proposed. The algorithm gives solutions with a minimum number of state variables instead of with minimal-cardinality next-state functions. Comparisons...
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A method for the state assignment of finite sequential machines is proposed. The algorithm gives solutions with a minimum number of state variables instead of with minimal-cardinality next-state functions. Comparisons between the results given by the proposed method and others previously reported have shown a clear superiority of the present algorithm in terms of silicon area, especially for big machines.< >
A directed search algorithm to minimize multiple-valued input functions with a single binary output is presented. A multiple binary output minimization problem is readily transformed to such a function. Further, any m...
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A directed search algorithm to minimize multiple-valued input functions with a single binary output is presented. A multiple binary output minimization problem is readily transformed to such a function. Further, any multiple-valued function can be transformed to a multiple binary output problem and hence to a function suited to the presented algorithm. The proposed algorithm can thus be applied to a broad class of minimization problems. Heuristics suitable for PLA (programmable logic arrays) realizations are used. Some results showing the performance of the algorithm are presented.< >
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