A report is given of how programmablelogic devices (PLDs) can be applied in custom logic designs using inexpensive software and programming hardware and be effectively integrated into a digital laboratory. Purdue Uni...
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A report is given of how programmablelogic devices (PLDs) can be applied in custom logic designs using inexpensive software and programming hardware and be effectively integrated into a digital laboratory. Purdue University's Electrical Engineering Technology program requires a two-semester freshman sequence in digital fundamentals. The first course covers combinational logic circuits and the second course primarily covers sequential logic circuits. Beginning with the Spring 1988 semester, the combinational logic course included electrically erasable PLDs as an additional component for logic-circuit design in the laboratory.< >
An algorithm is proposed to automatically generate rectilinear channel structures for rectilinear blocks. The two stages of automatic channel definition are: assignment of sides to supersides and assignment of supersi...
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An algorithm is proposed to automatically generate rectilinear channel structures for rectilinear blocks. The two stages of automatic channel definition are: assignment of sides to supersides and assignment of supersides to channels. The algorithm is coded in Pascal and has been incorporated into an automatic layout system as well as an interactive placement and channel editing system. The automatic channel definer has been tried on a number of real examples, and the results are shown.< >
A logical description of arrays is developed, indicating that it is possible to incorporate array data structures into a theory that builds on the conventional theory of lists. This theory provides a basis for the fun...
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A logical description of arrays is developed, indicating that it is possible to incorporate array data structures into a theory that builds on the conventional theory of lists. This theory provides a basis for the functional programming language Nial. An emphasis in the development of Nial has been to explore ways to integrate the logic programming paradigm with the functional-programming and array-handling capabilities of the language. By providing a logical basis for array theory, the authors have provided a formal basis for the development of a semantics for logic programming with arrays in Nial.< >
A method of estimating the area required to improve the testability of integrated circuits is described, and is illustrated by reference to programmable logic arrays (PLAs) with scan path applied. Parameters used in t...
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A method of estimating the area required to improve the testability of integrated circuits is described, and is illustrated by reference to programmable logic arrays (PLAs) with scan path applied. Parameters used in the models are derived from actual layouts. Results are given for PLAs with scan path, and for static RAMs incorporating scan path and built-in self-test (BIST) techniques. A stochastic model for estimating the global routing required on integrated circuits is presented, with results showing its use for predicting the routing area overhead due to test circuitry. A method of predicting the increased signal propagation delay due to added test circuitry is also given, together with the conditions for determining degradation in chip performance.< >
The authors present a defect-tolerant and fully testable programmablelogic array (PLA) that is based on dynamic redundancy, allowing for the repair of a defective chip. Special emphasis is placed on the location of d...
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The authors present a defect-tolerant and fully testable programmablelogic array (PLA) that is based on dynamic redundancy, allowing for the repair of a defective chip. Special emphasis is placed on the location of defects inside a PLA. The repair process consists of replacing a defect product term by a programmable spare one.< >
NCUBE applies all possible input patterns to each array cell while ensuring that the effects of incorrect transitions are observable at the array outputs. If the array is testable with a constant number of test vector...
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NCUBE applies all possible input patterns to each array cell while ensuring that the effects of incorrect transitions are observable at the array outputs. If the array is testable with a constant number of test vectors irrespective of its size (C-testable), then NCUBE generates the constant-size test set for the array. If the array cannot be tested with a constant number of test vectors, then the test size is proportional either to the number of rows or columns of the array or to the number of cells. In that case, NCUBE generates a minimal or near-minimal test set that depends on the size of the array.< >
A CMOS NOR-NOR testable PLA (CTPLA) which has a universal test set is discussed. Berkeley VLSI tools were used to implement and verify the design. The PLA contains an extra row and a column, along with a shift registe...
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A CMOS NOR-NOR testable PLA (CTPLA) which has a universal test set is discussed. Berkeley VLSI tools were used to implement and verify the design. The PLA contains an extra row and a column, along with a shift register and two cascades of exclusive-OR (EXOR) gates, to make it testable. The layout of the CTPLA was implemented such that the inherent regularity of the PLA can be maintained without undue compromise. A procedure which automatically generates the layout according to a given personalization was written. The test set detects all single stuck-at faults as well as crosspoint faults.< >
This paper describes a new sea of gates structure, usable for digital random logic, regular arrays, and analog cells. A dedicated design procedure features a full cell-abutment capability, together with channelless ro...
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This paper describes a new sea of gates structure, usable for digital random logic, regular arrays, and analog cells. A dedicated design procedure features a full cell-abutment capability, together with channelless routing. Design results are presented for several macroblocs, and compared with other semi-custom approaches. A set of rules is finally presented, which allows an automatic transformation of the sea of gates layout into a topologically equivalent full custom layout, converting semi-custom prototypes to full performance circuits.
Path programmablelogic (PPL) is a VLSI design methodology that is very efficient in the implementation of systems consisting of random logic, counters, and finite-state machines. Previous designs have shown that PPL ...
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Path programmablelogic (PPL) is a VLSI design methodology that is very efficient in the implementation of systems consisting of random logic, counters, and finite-state machines. Previous designs have shown that PPL does not efficiently allow the implementation of bus-oriented designs, such as microprocessors, arithmetic processors, and DSP (digital signal processor) chips. The authors present solutions that enable these architectures to be implemented more efficiently. The solutions are the introduction of automated routing and placement tools as well as the description of sophisticated PPL library cells. The implementation of a RISC (reduced-instruction-set computer) processor is used as a case study to verify the effectiveness of these changes to the existing PPL methodology.< >
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