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检索条件"主题词=Programmable Logic Arrays"

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Built-in self-test for large embedded CMOS folded PLAs

Built-in self-test for large embedded CMOS folded PLAs

引用

IEEE International Conference on Computer-Aided Design

作者： R. Dandapani R.K. Gulati D.K. Goel Department of Electrical Engineering University of Colorado Colorado Springs CO USA Ford Microelectronics Inc. Colorado Springs CO USA

A built-in self-test (BIST) design method for large embedded CMOS folded programmable logic arrays (PLAs) is presented that is based on a deterministic, function-independent structural method. It requires about half the testing time and comparable area overhead of deterministic BIST methods applied to corresponding nonfolded PLAs. Tests to detect stuck-at, bridging, cross-point and stuck-open faults are given.< >

关键词： Built-in self-test programmable logic arrays Circuit testing Circuit faults Very large scale integration Springs Design methodology Fault detection logic design logic testing

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Design of a PLU (programmable logic Unit), a new block for signal processing

Design of a PLU (Programmable Logic Unit), a new block for s...

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European Conference on Solid-State Circuits (ESSCIRC)

作者： P. de Bakker A. Delaruelle B. de Loore Philips Research Laboratories Eindhoven Netherlands

In this paper a new building block is described which can be used in Digital Signal Processing (DSP) IC's. This module, the PLU (programmable logic Unit), can perform dyadic operations (A v B, A ^ B, A © B ...), monadic operations (-A, -B , pass shiftr, ...) and bitwise operations (mask, scramble, ...). Furthermore, bitwise operations can be combined with monadic or dyadic operations. The PLU is easy to program as it is possible for users to define their own instruction set. In addition it is very effective with respect to area and speed. In order to make a flexible PLU, a parametrised module generator has been written. For a typical instance the total chip area necessary for an 8 bits PLU is 0.16 mm 2 in a 1.6 μm process. The delay of the PLU equals a two gate propagation delay.

关键词： Signal design logic design programmable logic arrays programmable logic devices Signal processing Digital signal processing Silicon Hardware Propagation delay Arithmetic

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UBIST version of the SYCO's control section compiler

UBIST version of the SYCO's control section compiler

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IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： K. Torki M. Nicolaidis A.A. Jerraya B. Courtois IMAG/TIM3 Grenoble France

The authors describe a design-for-testability strategy for the SYCO control section compiler (CPC). The SYCO CPC translates high-level descriptions into mask-level specification for hierarchical control sections, which are composed of a stack of control section slices, each one organized around a programmable logic array. The proposed design-for-testability scheme is called UBIST (unified built-in self-test) and ensures a high quality for all tests needed for integrated circuits (i.e. online and offline tests). The authors elucidate the concept of UBIST and show how to modify SYCO CPC data structure and its automatic layout synthesizer to generate UBIST control sections automatically and efficiently.< >

关键词： Circuit testing Integrated circuit testing programmable logic arrays Design for testability Automatic testing Automatic generation control Cascading style sheets Circuit faults Laboratories Data structures

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A new class of optimization algorithms for circuit design and modelling

A new class of optimization algorithms for circuit design an...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： M. Marchesi Dipartimento di Elettronica ed Autom. Ancona Univ. Italy

A class of optimization algorithms for finding the global minimum of functions of continuous variables is presented. These algorithms merge conventional local minima search strategies with the stimulated annealing (SA) technique. The rationale behind these algorithms is discussed, and a complete description is given of one of them, derived from the Hooke and Jeeves (1961) search method. Tests made on mathematical functions show an increase up to two orders of magnitudes in efficiency with respect to a conventional SA algorithm. An example of application to VLSI design is given.< >

关键词： Design optimization Circuit synthesis Simulated annealing Algorithm design and analysis Minimization Testing Circuit simulation Search methods Routing programmable logic arrays

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PLA based finite state machines using Johnson counters as state memories

PLA based finite state machines using Johnson counters as st...

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IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： R. Amann B. Eschermann U.G. Baitinger IBM Research Division Almaden Research Center San Jose CA USA University of California Berkeley Berkeley CA USA University of Karlsruhe Karlsruhe Germany

The authors present a novel state assignment technique for synchronous finite state machines (FSMs) that are implemented as single programmable logic arrays (PLAs) using Johnson counters as state memories. The goal is to minimize the number of product terms in the PLAs and thus the overall area of the FSMs. The authors use a three-step approach to achieve this. First, the FSM description is adapted to allow an optimal use of the computer properties; then the counter is embedded by ordering the internal states of the FSM; and finally the states are coded. The product term reductions obtained are, on the average 20% to 30% compared to conventional D-latch-based FSM implementations.< >

关键词： programmable logic arrays Automata Counting circuits Minimization logic design Design optimization Hardware Design methodology Combinational circuits Very large scale integration

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An architecture for electrically configurable gate arrays

An architecture for electrically configurable gate arrays

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Custom Integrated Circuits Conference (CICC)

作者： A. El Gamal J. Greene J. Reyneri E. Rogoyski K. El-Ayat A. Mohsen Actel Corporation Sunnyvale CA USA

A novel architecture for CMOS electrically configurable gate arrays using a two-terminal antifuse element is described. The architecture is extensible and can provide a level of integration comparable to mask-programmable gate arrays. This is accomplished by using a conventional gate array organization with rows of logic modules separated by wiring channels. Each channel contains segmented wiring tracks. The overhead need to program the antifuses is minimized by an addressing scheme that utilizes the wiring segments, pass transistors between adjacent segments, shared control lines, and serial addressing circuitry at the periphery of the array. By providing sufficient wiring tracks segmented into carefully chosen lengths and a logic module with a high degree of symmetry, fully automated placement and routing is facilitated.< >

关键词： Fuses Wiring programmable logic arrays logic arrays Routing Voltage Circuits logic programming Electric resistance Joining processes

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A modified approach to two-level logic minimization

A modified approach to two-level logic minimization

引用

IEEE International Conference on Computer-Aided Design

作者： A.A. Malik R.K. Brayton A.R. Newton A.L. Sangiovanni-Vincentelli Department of Electrical Engineering and Computer Sciences University of California Berkeley USA

A methodology in which it is not necessary to compute the entire offset is presented, that still provides a global picture. This scheme has been implemented in ESPRESSO with an interface to the multilevel minimization environment MIS. Initial results show that for functions for which the ratio of the size of the cover to the size of the don't care set is small, the new approach is much faster. The initial interest was to use this mainly in a multilevel logic synthesis system where the desired don't care sets are typically large. Some results in this environment are given, and the new scheme is compared with ESPRESSO.< >

关键词： Minimization methods Testing Boolean functions Contracts programmable logic arrays

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On Discrete Inner-Outer and Spectral Factorizations

On Discrete Inner-Outer and Spectral Factorizations

引用

American Control Conference (ACC)

作者： Cheng-Chih Chu Jet Propulsion Laboratory California Institute of Technology Pasadena CA USA

In this paper, reliable algorithms are developed to perform inner-outer, coprime, and spectral factorizations for discrete FDLTI systems. It is shown that the discrete algebraic Riccati equation plays an important role in obtaining state-space representations for all key factorizations. The implementation of algorithms can be carried out efficiently using real matrix operations.

关键词： Riccati equations Propulsion Laboratories programmable logic arrays Sufficient conditions State feedback Neural networks

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Input assignment algorithm for decoded-PLAs with multi-input decoders

Input assignment algorithm for decoded-PLAs with multi-input...

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IEEE International Conference on Computer-Aided Design

作者： Kuang-Chien Chen S. Muroga Department of Computer Science University of Illinois Urbana-Champaign Urbana IL USA

A heuristic algorithm for assigning input variables to the decoders of a decoded-programmable logic array (PLA) is presented. In this algorithm, the number of inputs to each decoder is not restricted to two and the area overhead incurred by using multi-input decoders is considered in the cost function. Experimental results show that the areas of multi-input decoded-PLAs designed by this algorithm are smaller in many cases than those of decoded-PLAs with two-input decoders or standard PLAs.< >

关键词： Decoding programmable logic arrays Input variables Computer science Heuristic algorithms Cost function Algorithm design and analysis Dynamic programming Very large scale integration logic design

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A 9000-gate user-programmable gate array

A 9000-gate user-programmable gate array

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Custom Integrated Circuits Conference (CICC)

作者： H.-C. Hsieh K. Dong J.Y. Ja R. Kanazawa L.T. Ngo L.G. Tinkey W.S. Carter R.H. Freeman Xilinx Inc. San Jose CA USA

The 900-gate XC3090 CMOS user-programmable gate array is the largest member of a family of devices based on a second-generation logic cell array (LCA) architecture. This architecture features three types of user-configurable elements: an interior array of logic blocks, a perimeter of input/output (I/O) blocks, and interconnection resources. Configuration is established by programming internal static memory cells that determine the logic functions and interconnections. An IC design and layout methodology based on modularity combined with the use of advanced processing technology allowed this architecture to be extended to 9000 usable gates. Architectural resources were designed to allow for a range of logic densities without compromising overall performance. User-programmable gate arrays can be used in place of conventional, mask-programmed gate arrays for the majority of digital designs.< >

关键词： logic arrays logic programming CMOS logic circuits programmable logic arrays logic devices Functional programming logic functions Integrated circuit layout Design methodology logic design

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