The 900-gate XC3090 CMOS user-programmable gate array is the largest member of a family of devices based on a second-generation logic cell array (LCA) architecture. This architecture features three types of user-confi...
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The 900-gate XC3090 CMOS user-programmable gate array is the largest member of a family of devices based on a second-generation logic cell array (LCA) architecture. This architecture features three types of user-configurable elements: an interior array of logic blocks, a perimeter of input/output (I/O) blocks, and interconnection resources. Configuration is established by programming internal static memory cells that determine the logic functions and interconnections. An IC design and layout methodology based on modularity combined with the use of advanced processing technology allowed this architecture to be extended to 9000 usable gates. Architectural resources were designed to allow for a range of logic densities without compromising overall performance. User-programmable gate arrays can be used in place of conventional, mask-programmed gate arrays for the majority of digital designs.< >
Using custom circuitry, a higher level of performance has been achieved for a new implementation of the Scalable Processor Architecture (SPARC). A CY601 processor (integer unit), running at a clock rate of 25-33 MHz, ...
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Using custom circuitry, a higher level of performance has been achieved for a new implementation of the Scalable Processor Architecture (SPARC). A CY601 processor (integer unit), running at a clock rate of 25-33 MHz, implements the complete set of SPARC instructions in a 0.8- mu m CMOS technology. An overview is given of the processor chip and its interface to the external cache, floating-point unit, and a generic coprocessor.< >
The results of a formal logic verification system implemented as part of the multilevel logic synthesis system MIS are discussed. Combinational logic verification involves checking two networks for functional equivale...
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The results of a formal logic verification system implemented as part of the multilevel logic synthesis system MIS are discussed. Combinational logic verification involves checking two networks for functional equivalence. Techniques that flatten networks or use cube enumeration and simulation cannot be used with functions that have very large cube covers. Binary decision diagrams (BDDs) are canonical representations for Boolean functions and offer a technique for formal logic verification. However, the size of BDDs is sensitive to the variable ordering. Ordering strategies based on the network topology are considered. Using these strategies with BDDs, it has been possible to carry out formal verification for a larger set of networks than with existing verification systems. The present method proved significantly faster on the benchmark set of examples tested.< >
The author presents a hybrid programmable-logic array (PLA) design-for-testability technique that requires negligible hardware overhead and still preserves the property of ease of test generation. The key idea is to f...
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The author presents a hybrid programmable-logic array (PLA) design-for-testability technique that requires negligible hardware overhead and still preserves the property of ease of test generation. The key idea is to further utilize the 'don't care' assignment by introducing the control of both true and complement bits of some inputs to meet the requirement of distance-2 test sets. This approach is applied to the BARNEW PLA, and results support the claim that the hardware overhead of this technique is negligible and the ease of test generation is preserved.< >
A monolithic 12-bit, 667-ns, two-step flash analog-to-digital converter has been implemented in standard 3- mu m CMOS technology. A 12-bit accurate reference bank incorporating a switched-capacitor integrator and a ba...
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A monolithic 12-bit, 667-ns, two-step flash analog-to-digital converter has been implemented in standard 3- mu m CMOS technology. A 12-bit accurate reference bank incorporating a switched-capacitor integrator and a bank of 66 sample-and-hold amplifiers is discussed. Self-calibration techniques are used to correct for the converter's gain and offset errors.< >
The author describes the geometric arithmetic parallel processor (GAPP) processing element, the array of processors and its control, the system into which any array is embedded, the interface to external data sources ...
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The author describes the geometric arithmetic parallel processor (GAPP) processing element, the array of processors and its control, the system into which any array is embedded, the interface to external data sources and data sinks, and the software development environment. Typical applications are then discussed. The GAPP cell, chip, array, systems and module are described.< >
A parallel scan design for finite-state machines (FSMs) was proposed by S.M. Reddy and R. Dandapani (1987), and analyzed for critical parameters such as area, delay, and active devices. The authors study the design pr...
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A parallel scan design for finite-state machines (FSMs) was proposed by S.M. Reddy and R. Dandapani (1987), and analyzed for critical parameters such as area, delay, and active devices. The authors study the design presented by Reddy and Dandapani for test parameters including increase in test vectors for both cross-point and single stuck-at faults, fault coverage, and time taken for fault detection. It is shown that even though there is an increase in the number of test vectors due to additional hardware, the testing time is reduced to the parallelism of the design. NMOS technology is used in the analysis.< >
An advanced high-voltage CMOS process has been developed for custom products with on-chip electrically erasable programmable read-only memory (EEPROM). The minimum feature size is 1.2 mu m. Process adjustments to achi...
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An advanced high-voltage CMOS process has been developed for custom products with on-chip electrically erasable programmable read-only memory (EEPROM). The minimum feature size is 1.2 mu m. Process adjustments to achieve >18-V high-voltage operation are explained in detail. Performance of short-channel transistors with L/sub eff/<1.0 mu m is also described. The Motorola FETMOS EEPROM cell characteristics and reliability are discussed. Microprocessor chips with up to 68K bits of EEPROM have been fabricated using this process.< >
A silicon compiler able to synthesize concurrent VLSI systems is described. This compiler differs from most existing silicon compilers as there is no target architecture, and yet results have shown that it performs re...
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A silicon compiler able to synthesize concurrent VLSI systems is described. This compiler differs from most existing silicon compilers as there is no target architecture, and yet results have shown that it performs reasonably well for a range of applications. It features a novel technique for control-step partitioning based on a precedence graph. Concurrency is detected and extracted from the input description in order to generate a fast implementation. The graph, which corresponds to a state diagram of the circuit, is further optimized using a simple rule-based approach. A controller able to control any number of concurrent processes, based on a synchronous token-passing mechanism, is generated. Control signals are submitted to two-level and multilevel logic minimization, and they can be implemented either as a programmable logic arrays (PLA) or with standard cells. The data path is generated as a netlist of technology-independent parameterized cells which are mapped into cells from a library by a module binder. The final layout is automatically generated by placement-and-routing programs.< >
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