咨询与建议

限定检索结果

文献类型

  • 3,664 篇 会议
  • 775 篇 期刊文献

馆藏范围

  • 4,439 篇 电子文献
  • 0 种 纸本馆藏

日期分布

学科分类号

  • 1,149 篇 工学
    • 657 篇 电气工程
    • 362 篇 计算机科学与技术...
    • 154 篇 电子科学与技术(可...
    • 149 篇 材料科学与工程(可...
    • 129 篇 信息与通信工程
    • 80 篇 软件工程
    • 79 篇 化学工程与技术
    • 78 篇 控制科学与工程
    • 68 篇 仪器科学与技术
    • 39 篇 核科学与技术
    • 33 篇 机械工程
    • 27 篇 生物医学工程(可授...
    • 11 篇 测绘科学与技术
    • 11 篇 生物工程
    • 10 篇 网络空间安全
    • 8 篇 石油与天然气工程
    • 8 篇 环境科学与工程(可...
    • 7 篇 光学工程
    • 7 篇 动力工程及工程热...
  • 251 篇 理学
    • 109 篇 化学
    • 80 篇 物理学
    • 38 篇 生物学
    • 23 篇 系统科学
  • 68 篇 医学
    • 43 篇 临床医学
    • 15 篇 基础医学(可授医学...
    • 9 篇 药学(可授医学、理...
  • 47 篇 管理学
    • 35 篇 管理科学与工程(可...
  • 21 篇 农学
    • 8 篇 农业资源与环境
  • 15 篇 教育学
    • 14 篇 教育学
  • 13 篇 文学
    • 12 篇 新闻传播学
  • 3 篇 艺术学
  • 2 篇 军事学
  • 1 篇 经济学
  • 1 篇 法学

主题

  • 4,439 篇 programmable log...
  • 1,072 篇 field programmab...
  • 530 篇 programmable log...
  • 476 篇 hardware
  • 473 篇 logic devices
  • 438 篇 logic design
  • 399 篇 logic arrays
  • 335 篇 very large scale...
  • 308 篇 logic circuits
  • 302 篇 routing
  • 298 篇 computer archite...
  • 291 篇 circuit testing
  • 277 篇 costs
  • 275 篇 logic testing
  • 247 篇 switches
  • 218 篇 computer science
  • 211 篇 circuit synthesi...
  • 204 篇 table lookup
  • 201 篇 boolean function...
  • 200 篇 reconfigurable l...

机构

  • 36 篇 institute of com...
  • 31 篇 institute of com...
  • 29 篇 xilinx inc. san ...
  • 23 篇 people''s libera...
  • 21 篇 department of el...
  • 18 篇 school of electr...
  • 17 篇 institute of com...
  • 16 篇 altera corporati...
  • 13 篇 ibm thomas j. wa...
  • 12 篇 philips research...
  • 12 篇 actel corporatio...
  • 12 篇 logic vision inc...
  • 11 篇 department of co...
  • 10 篇 institute of tel...
  • 9 篇 department of el...
  • 9 篇 department of el...
  • 9 篇 department of el...
  • 9 篇 at and t bell la...
  • 9 篇 institute of met...
  • 8 篇 intel corporatio...

作者

  • 19 篇 m. renovell
  • 15 篇 m.a. perkowski
  • 14 篇 f. lombardi
  • 14 篇 r.k. brayton
  • 12 篇 y. zorian
  • 12 篇 ming chen
  • 12 篇 xie ning
  • 12 篇 a. sangiovanni-v...
  • 12 篇 jianjiang lu
  • 12 篇 g. van der plas
  • 12 篇 b.j. falkowski
  • 10 篇 t. sasao
  • 10 篇 j. rose
  • 9 篇 c.l. liu
  • 9 篇 c. stroud
  • 9 篇 f. pla
  • 9 篇 s.j.e. wilton
  • 9 篇 j.m. portal
  • 9 篇 j. figueras
  • 9 篇 a.r. newton

语言

  • 4,330 篇 英文
  • 81 篇 其他
  • 27 篇 中文
  • 1 篇 土耳其文
检索条件"主题词=Programmable Logic Arrays"
4439 条 记 录,以下是4021-4030 订阅
排序:
CMOS customer implementation of the SPARC architecture
CMOS customer implementation of the SPARC architecture
收藏 引用
IEEE Compcon
作者: M. Namjoo F. Abu-Nofal D. Carmean R. Chandramouli Y. Chang J. Goforth W. Hsu R. Iwamoto C. Murphy U. Naot M. Parkin J. Pendleton C. Porter J. Reaves R. Reddy G. Swan D. Tinker P. Tong L. Yang Sun Microsystems Inc. Mountain View CA USA Cypress Semiconductors Inc. San Jose CA USA
Using custom circuitry, a higher level of performance has been achieved for a new implementation of the Scalable Processor Architecture (SPARC). A CY601 processor (integer unit), running at a clock rate of 25-33 MHz, ... 详细信息
来源: 评论
logic verification using binary decision diagrams in a logic synthesis environment
Logic verification using binary decision diagrams in a logic...
收藏 引用
IEEE International Conference on Computer-Aided Design
作者: S. Malik A.R. Wang R.K. Brayton A. Sangiovanni-Vincentelli Department of Electrical Engineering and Computer Sciences University of California Berkeley CA USA Dept. of Electr. Eng. & Comput. Sci. California Univ. Berkeley CA USA
The results of a formal logic verification system implemented as part of the multilevel logic synthesis system MIS are discussed. Combinational logic verification involves checking two networks for functional equivale... 详细信息
来源: 评论
Relay Ladder logic Design Using The Language Of Regular Expressions
Relay Ladder Logic Design Using The Language Of Regular Expr...
收藏 引用
Annual Conference of Industrial Electronics Society
作者: R. Devanathan School of Electrical and Electronic Engineering Nanyang Technological Institute Singapore
来源: 评论
A testable PLA design with low overhead and ease of test generation
A testable PLA design with low overhead and ease of test gen...
收藏 引用
IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)
作者: J.-Y. Jou AT&T Bell Labaratories Murray Hill NJ USA
The author presents a hybrid programmable-logic array (PLA) design-for-testability technique that requires negligible hardware overhead and still preserves the property of ease of test generation. The key idea is to f... 详细信息
来源: 评论
A 667 ns, 12-bit two-step flash ADC
A 667 ns, 12-bit two-step flash ADC
收藏 引用
Custom Integrated Circuits Conference (CICC)
作者: D.A. Kerth N.S. Sooch E.J. Swanson Crystal Semiconductor Corporation Austin TX USA
A monolithic 12-bit, 667-ns, two-step flash analog-to-digital converter has been implemented in standard 3- mu m CMOS technology. A 12-bit accurate reference bank incorporating a switched-capacitor integrator and a ba... 详细信息
来源: 评论
The geometric arithmetic parallel processor
The geometric arithmetic parallel processor
收藏 引用
Frontiers of Massively Parallel Computation
作者: E.L. Cloud Martin Marietta Electronic Systems Orlando FL USA
The author describes the geometric arithmetic parallel processor (GAPP) processing element, the array of processors and its control, the system into which any array is embedded, the interface to external data sources ... 详细信息
来源: 评论
An advanced high voltage CMOS process for custom logic circuits with embedded EEPROM
An advanced high voltage CMOS process for custom logic circu...
收藏 引用
Custom Integrated Circuits Conference (CICC)
作者: K.Y. Chang S. Cheng K.-M. Chang J. Chalmers C. Swift J. Yeargain APRDL Motorola Inc. Austin TX USA
An advanced high-voltage CMOS process has been developed for custom products with on-chip electrically erasable programmable read-only memory (EEPROM). The minimum feature size is 1.2 mu m. Process adjustments to achi... 详细信息
来源: 评论
Computer aided test synthesis for a parallel scan design of finite state sequential machines
Computer aided test synthesis for a parallel scan design of ...
收藏 引用
IEEE Region 5 Annual Technical Conference
作者: S.N. Iyengar R. Dandapani S.M. Reddy Department of Electrical Engineering University of Colorado Colorado Springs USA Dept. of Electr. Eng. Colorado Univ. Colarado Springs CO USA Department of Electrical and Computer Engineering University of Iowa USA
A parallel scan design for finite-state machines (FSMs) was proposed by S.M. Reddy and R. Dandapani (1987), and analyzed for critical parameters such as area, delay, and active devices. The authors study the design pr... 详细信息
来源: 评论
A graph-based silicon compiler for concurrent VLSI systems
A graph-based silicon compiler for concurrent VLSI systems
收藏 引用
CompEuro
作者: R. Bergamaschi D.J. Allerton Department of Electronics and Computer Science University of Southampton Southampton UK
A silicon compiler able to synthesize concurrent VLSI systems is described. This compiler differs from most existing silicon compilers as there is no target architecture, and yet results have shown that it performs re... 详细信息
来源: 评论
Detection of control flow errors using signature and checking instructions
Detection of control flow errors using signature and checkin...
收藏 引用
IEEE International Test Conference
作者: J. Sosnowski Institute of Computer Science Warsaw Technical University Warsaw Poland
An approach is presented to the online detection of control flow errors caused by transient and intermittent faults in microprocessor systems. It is based on the idea of signatured instruction streams. Signatures are ... 详细信息
来源: 评论