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检索条件"主题词=Programmable Logic Arrays"

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An efficient logic block interconnect architecture for user-reprogrammable gate array

An efficient logic block interconnect architecture for user-...

引用

Custom Integrated Circuits Conference (CICC)

作者： K. Kawana H. Keida M. Sakamoto K. Shibata I. Moriyama LSI Research Center Kawasaki Steel Corporation Chiba Japan

A novel architecture for an SRAM-based user-reprogrammable gate array which consists of programmable logic elements (PLEs), switching stations (SSs), wirings, and input/output blocks (IOBs) is discussed. The SS is designed to connect its neighboring PLEs and/or IOBs through only one NMOS pass transistor to maintain a sufficient signal level and reduce the delay in signal propagation. Hidden interconnection networks which directly merge neighboring PLEs were adopted to expand the number of inputs and product terms of combinational logic, and allow the construction of a parallel-to-serial/serial-to-parallel converter without using SSs. A fabricated CMOS prototype chip includes an 8 Kbit 50 ns temporary storage memory which is programmable to the random access mode or the FIFO mode with a word length of 4 bit or 8 bit.< >

关键词： logic arrays programmable logic arrays logic devices programmable logic devices Flip-flops Circuits Wiring Random access memory Switches Testing

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A 76 MHz programmable logic sequencer

A 76 MHz programmable logic sequencer

引用

IEEE International Conference on Solid-State Circuits (ISSCC)

作者： C. Sung P. Sasaki R. Leung Y.M. Chu K. Le G. Conner R. Lane J.L. de Jong R. Cline Application Specific Products Division Signetics Company Sunnyvale CA USA Advanced Technology Development Signetics Company Sunnyvale CA USA

The authors describe a BiCMOS programmable logic sequencer which provides reduced power, has functional density and flexibility similar to that of CMOS, and maintains speed as high as that of bipolar devices. The device is organized as 16 inputs, 48 product terms, and 8 registered outputs. Both logic AND and OR arrays are designed for user-programmability, enabling any chosen product term to be shared as a common sum-of-products by all of the outputs without resorting to a large number of product terms. A separate BiCMOS programming path test chip, compatible with this device, was manufactured simultaneously and evaluated separately. The equivalent gate count for this device is approximately 1000 gates. A maximum operating frequency of 76 Mhz, with 6-ns clock to output delay and 7-ns input setup time at a power dissipation of 370 mW, has been achieved. The process used to fabricate this device is a merged bipolar and CMOS technology featuring 1.9- mu m L/sub eff/ and 1.2- mu m*3- mu m emitter, three-layer metal and single-layer polycide for interconnections, TiW fuses, PtSi Schottky diodes, and polysilicon resistors.< >

关键词： programmable logic arrays programmable logic devices CMOS logic circuits logic devices BiCMOS integrated circuits logic arrays CMOS technology logic design logic programming Testing

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Towards understanding requirement evolution in a software product line an industrial case study

Towards understanding requirement evolution in a software pr...

引用

IEEE International Workshop on the Twin Peaks of Requirements and Architecture (Twin Peaks)

作者： Yijian Wu Didar Zowghi Xin Peng Wenyun Zhao School of Computer Science Fudan University Shanghai China Faculty of Engineering and Information Technology University of Technology Sydney Australia

In most software development practices, software requirements and architecture are addressed simultaneously. The architecture may grow based on a core specification of requirements, and the requirements may also be elicited incrementally as the architecture gets more and more concrete. In this paper, we present a case study on the development history of Wingsoft Examination System Product Line (WES-PL), an active, industrial software product line with a history of more than eight years. We focus on 10 member products, 51 major versions that have been delivered to customer or archived in the repository between December 2003 and May 2012, by tracing both requirement and architectural changes. We identify a requirement change classification from the viewpoint of architectural impact. We claim that software requirements are negotiated and may be guided by existing software architecture design, especially in the process of software product line development. Product strategy requirements play an important role in marketing requirement negotiation. We also find typical evidences showing that a product leader or architect has to make difficult decisions to keep a balance between marketing requirements from customer-side and software architectural design from his own side.

关键词： programmable logic arrays Computer architecture Software History Cloning Switches Graphical user interfaces

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Next Generation FPGA's Provide New System-Level Integration Solutions

Next Generation FPGA's Provide New System-Level Integration ...

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Electro

作者： K.A. Owyang Actel Corporation Sunnyvale CA USA

Actel Corporation's ACT 2 family of Field programmable Gate arrays (FPGA) is a significant advancement in density and performance for programmable logic devices. This latest generation of FPGAs provides design solutions for system-level integration that have not been previously available in the FPGA marketplace. Upon introduction, the A1280, the first and largest member of the ACT 2 family, found system-level applications in the consumer electronics industry at Videonics Corporation. The application of the A1280 in the Videonics Video Equalizer is described in this paper.

关键词： Field programmable gate arrays logic devices CMOS process Routing programmable logic arrays Packaging CMOS logic circuits Pins Flip-flops Delay

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Computer-Aided Custom LSI Design with the ULA

Computer-Aided Custom LSI Design with the ULA

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European Conference on Solid-State Circuits (ESSCIRC)

作者： B.D. Prazic J.A.C. Stenton M.H. Manley P.J. Mole GEC-Marconi Hirst Research Centre Wembley UK

A complete suite of computer programs is described for custom LSI design with the ULA. The Array is designed in silicon-gate CMOS/SOS and contains 512 cells and 64 bonding pads.

关键词： Large scale integration CMOS logic circuits logic design logic circuits Integrated circuit interconnections Inverters Circuit simulation logic arrays programmable logic arrays CMOS technology

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The Learning of Reconfigurable Computing in the Computer Engineering Program

The Learning of Reconfigurable Computing in the Computer Eng...

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Frontiers in Education (FIE) Conference

作者： Edson Pedro Ferlin Valfredo Pilla Computer Engineering Department Centro Universitário Positivo - UnicenP Curitiba PR Brazil Professor Computer Engineering Department Centro Universitário Positivo - UnicenP vpilla@unicenp.edu.br

The reconfigurable computing has an increasing importance in the computational solutions because of its two main characteristics: performance and flexibility. This became possible with the technological advance of the complex programmable logic devices (CPLDs) and the field programmable gate array (FPGAs), which makes possible an increasing level of system integration (hardware and software). This integration can allow the construction of a complex system in a single device, the system on chip (SoC) technology. This is a multidisciplinary area, because it involves digital systems projects (some time analog systems also), firmware and operational systems development, beyond the specific knowledge of the areas of the systems applications. For this reasons the reconfigurable computation became part of the computer engineer formation. It is imperative that the new professionals have complete domain of this technology to be able to integrate it in the new computational systems. These computational systems reach a wide range of applications, from high performance computing to embedded systems, personal and mobile computing, to entertainment and mobile communication. In this direction, we present the evolution that happened in the Computer Engineering Program at UnicenP from the adoption of the technology of CPLDs and FPGAs in several courses, and the inclusion of a specific reconfigurable computing course

关键词： Field programmable gate arrays High performance computing programmable logic arrays Application software Embedded computing programmable logic devices Field programmable analog arrays Hardware System-on-a-chip Digital systems

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Routing algorithms for programmable logic device design and manufacturing test development

Routing algorithms for programmable logic device design and ...

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International Automatic Testing Conference, AUTOTESTCON

作者： J.R. Heath N.J. Vocke C.E. Stroud J. Emmert University of Kentucky USA Intel Inc. USA University of North Carolina Charlotte USA

A Computer Aided Design (CAD) tool consisting of two new interconnect network routing algorithms is developed. It was developed to assist in manufacturing test development for any programmable logic Device (PLD) such as Complex programmable logic Devices (CPLDs) and/or Field programmable Gate Array (FPGA) devices which utilize any interconnect network structure whose definition/connectivity and control can be described in a presented manner. The CAD tool utilizing the new routing algorithms supports manual and semiautomatic explicit, non-explicit, and net routing and was extensively tested on the interconnect networks of the Cypress Delta39K/sup TM/ series CPLD for the purpose of manufacturing testing of the programmable interconnect networks within the device as well as all programmable logic functions of the device. The two routing algorithms were developed and experimentally proved to work correctly with the best one chosen based on both theoretical and experimental complexity analysis and the particular routing scenario to be solved. The resultant routing CAD tool will produce the configuration bits necessary to program or configure PLD devices for the extensive tests that must be applied to ensure that the manufactured PLDs are defect-free. The router CAD tool can also be extensively used in the verification of the design process of PLDs as verified via experimental testing.

关键词： Routing programmable logic devices Algorithm design and analysis Design automation logic testing Field programmable gate arrays programmable logic arrays Computer aided manufacturing Computer networks logic functions

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Large-Scale FPAA Devices for Signal Processing Applications

Large-Scale FPAA Devices for Signal Processing Applications

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International Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： Christopher M. Twigg Paul Hasler David V. Anderson Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA USA

We present a viewpoint showing that analog signal processing approaches are becoming configurable and programmable like their digital counterparts, while retaining a huge computational efficiency, for a given power budget, compared to their digital counterparts. We present recent results in programmable and configurable analog signal processing describing the widespread potential of these approaches. We also discuss issues with configurable systems, including size, power, and computational tradeoffs, as well as address the computational efficiency of these approaches.

关键词： Large-scale systems Field programmable analog arrays Signal processing Digital signal processing Analog computers Computational efficiency Field programmable gate arrays programmable logic arrays Signal design Signal processing algorithms

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Multi-level reconfiguration in the DANAH assistive system

Multi-level reconfiguration in the DANAH assistive system

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IEEE International Conference on Systems, Man and Cybernetics

作者： Saïd Lankri Pascal Berruet Jean-Luc Philippe Lab-STICC Laboratory European University of Brittany-UBS Lorient France

Nowadays, interaction with our surrounding environment has increased due to the presence of numerous devices that provide us with services. This is especially true in Smart Homes and can be of great help for the disabled people and the elderly that can no longer perform daily tasks they used to. However, in case of failure, corrective actions can be heavy to take, thus the need for the system to recover by itself and ensure service availability. Service availability is provided through service reconfiguration. This papers deals with service reconfiguration in smart homes. It presents a multi-level approach in which both off-line and on-line reconfiguration schemes are used to gradually recover from failed services. Static, effect-based, path and resource reconfiguration levels are described. They have been successfully implemented in the DANAH assistive system, which combines both navigation and service provision for smart homes.

关键词： Smart homes Availability Field programmable gate arrays Hardware Pervasive computing Navigation Space technology programmable logic arrays Intelligent sensors Ambient intelligence

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Design methodology for a 1.0 GHz microprocessor

Design methodology for a 1.0 GHz microprocessor

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IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： S. Posluszny N. Aoki D. Boerstler J. Burns S. Dhong U. Ghoshal P. Hofstee D. LaPotin K. Lee D. Meltzer H. Ngo K. Nowka J. Silberman O. Takahashi I. Vo IBM Austin Research Laboratory Austin TX USA International Business Machines Corp Armonk NY US

This paper describes the design methodology used to build an experimental 1.0 GigaHertz PowerPC integer microprocessor at IBM's Austin Research Laboratory. The high frequency requirements dictated the chip composition to be almost entirely custom macros using dynamic circuit techniques. The methodology presented will cover design and verification tools as well as circuit constraints and microarchitecture philosophy. The microarchitecture, circuits and tools were defined by the high frequency requirements of the processor as well as the aggressive design schedule and size of the design team.

关键词： Design methodology Microprocessors programmable logic arrays logic design Frequency Timing Latches logic circuits Read only memory Microarchitecture

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