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检索条件"主题词=Programmable Logic Arrays"
4439 条 记 录,以下是4031-4040 订阅
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Scheduling Turbofan Engine Control Set Points by Semi-Infinite Optimization
Scheduling Turbofan Engine Control Set Points by Semi-Infini...
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American Control Conference (ACC)
作者: D.M. Stimler Control Systems Laboratory GE Corporate Research and Development Center Schenectady NY USA
It is shown that modern Semi-Infinite Optimization Methods provide a powerful method for determining the operating schedules of control set points for advanced turbofan engines. It is shown that these methods give the... 详细信息
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A defect-tolerant and fully testable PLA
A defect-tolerant and fully testable PLA
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Design Automation Conference
作者: N. Wehn M. Glesner K. Caesar P. Mann A. Roth Institut fuer Halbleitertechnik Fachgebiet Halbleiterschaltungstechnik Technische Hochschule Darmstadt Darmstadt Germany
The authors present a defect-tolerant and fully testable programmable logic array (PLA) that allows the repair of a defective chip. The repair process is described. Special emphasis is placed on the location of defect... 详细信息
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A microprocessor-based development system for digital systems design education
A microprocessor-based development system for digital system...
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IEEE Southeastcon
作者: M.C. Woodfill W.T. Neumann Department of Computer Science Arizona State University Tempe AZ USA
A multiuser development system is presented that was developed specifically for use in the instruction of digital systems design. This system affords students a unique opportunity to examine the actual implementation ... 详细信息
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A 50mhz Cmos programmable logic Device
A 50mhz Cmos Programmable Logic Device
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IEEE International Conference on Solid-State Circuits (ISSCC)
作者: Pathak Vider Douglass Arreola Mehta Cypress Semiconductors Inc. San Jose CA USA
来源: 评论
A massively parallel systolic array processor system
A massively parallel systolic array processor system
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Proceedings of the International Conference on Systolic arrays
作者: R.E. Morley T.J. Sullivan Electronic Systems and Signals Research Laboratory Department of Electrical Engineering Washington University Saint Louis MO USA
The design of a massively parallel processor, comprised of 2304-bit-serial processor elements arranged in a 48 by 48 systolic array, is described. The system consists of the processor array, a microstore controller, a... 详细信息
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A fast algorithm for the optimal state assignment of large finite state machines
A fast algorithm for the optimal state assignment of large f...
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IEEE International Conference on Computer-Aided Design
作者: D. Varma E.A. Trachtenberg ECE Department Drexel University Philadelphia PA USA
A state-assignment procedure is presented that uses only abstract complexity criteria and produces assignments that are not targeted toward particular implementations. It produces networks similar in complexity to tho... 详细信息
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A 120 K-gate usable CMOS sea of gates packing 1.3 M transistors
A 120 K-gate usable CMOS sea of gates packing 1.3 M transist...
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Custom Integrated Circuits Conference (CICC)
作者: Y. Suehiro D. Miura M. Naitoh S. Tsutsumi T. Shirato Fujitsu Laboratories Limited Kawasaki Japan
A CMOS sea of gates with 160 K basic cells for random logic and memories is reported. Because of the unique architecture, the LSI offers flexible configuration of RAMs, ROMs, and PLAs (programmable logic arrays) with ... 详细信息
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Parallel implementation of real-time control programs
Parallel implementation of real-time control programs
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IEEE Conference on Decision and Control
作者: P.L. Shaffer Control Systems Laboratory GE Corporate Research and Development Center Schenectady NY USA
Two turbojet engine control programs were analyzed for potential parallelism. Both were subjected to global, hierarchical, large-grain data-flow analysis, using internally developed data-flow analysis tools. Execution... 详细信息
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Performance enhancements in BOLD using 'implications'
Performance enhancements in BOLD using 'implications'
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IEEE International Conference on Computer-Aided Design
作者: G. Hachtel R. Jacoby P. Moceyunas C. Morrison Department of Electrical and Computer Engineering University of Colorado Boulder USA
Uses of implied network values or conditions in the context of multilevel logic synthesis are presented. The use of these implications has resulted in performance-enhanced versions, ESPRESSOMLT2 and MLTAUT2, of the tw... 详细信息
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Fast efficient algorithms for the factoring of multiple output logic functions
Fast efficient algorithms for the factoring of multiple outp...
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IEEE International Symposium on Circuits and Systems (ISCAS)
作者: H.-J. Mathony U.G. Baitinger Institute of Information Processing Techniques University of Karlsruhe Germany
Factoring is a technique for converting a two-level circuit description to a logical equivalent multilevel form to achieve economy or to meet fan-in and fan-out limitations of the given technology. The authors describ... 详细信息
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