It is shown that modern Semi-Infinite Optimization Methods provide a powerful method for determining the operating schedules of control set points for advanced turbofan engines. It is shown that these methods give the...
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It is shown that modern Semi-Infinite Optimization Methods provide a powerful method for determining the operating schedules of control set points for advanced turbofan engines. It is shown that these methods give the engineer considerable design freedom and shows how these methods can be used to develop engine schedules which optimize complex performance objectives and explicitly satisfy performance requirements on engine variables. This approach is also shown to provide insights as to the limits of engine performances and the control requirements of the engine. These methods are illustrated by determining portions of the steady state and transient operating schedules of a state-of-the-art single bypass turbofan engine.
The authors present a defect-tolerant and fully testable programmablelogic array (PLA) that allows the repair of a defective chip. The repair process is described. Special emphasis is placed on the location of defect...
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The authors present a defect-tolerant and fully testable programmablelogic array (PLA) that allows the repair of a defective chip. The repair process is described. Special emphasis is placed on the location of defects inside a PLA. The defect location mechanism is completely topological and circuit-independent and therefore easy to adapt to existing PLA generators. Yield considerations for this type of PLA are presented.< >
A multiuser development system is presented that was developed specifically for use in the instruction of digital systems design. This system affords students a unique opportunity to examine the actual implementation ...
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A multiuser development system is presented that was developed specifically for use in the instruction of digital systems design. This system affords students a unique opportunity to examine the actual implementation of advanced architectural features in an environment that is far more accessible than comparable designs using state-of-the-art microprocessors. The DSL System 990 has been used in the classroom for two years, and good results have been obtained. The students show the ability to effectively interact with the system as both users and designers.< >
The design of a massively parallel processor, comprised of 2304-bit-serial processor elements arranged in a 48 by 48 systolic array, is described. The system consists of the processor array, a microstore controller, a...
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The design of a massively parallel processor, comprised of 2304-bit-serial processor elements arranged in a 48 by 48 systolic array, is described. The system consists of the processor array, a microstore controller, and a host computer interface. Program development tools are available on the host computer. The processor array uses 32 NCR GAPP (Geometric Arithmetic Parallel Processor) microprocessor chips, while the microstore controller is implemented with a TMS32010 DSP chip and TTL (transistor-transistor logic) circuitry. Utilizing the nearest neighbor communication capabilities of the GAPP, the array receives data from the host at the south end of the array, outputs data to the host at the north edge of the array, and can wrap data between either the east and west or north and south edges. The array can also be configured as a linear array of 2304 processor elements. The microstore controller interfaces with the host and facilitates downloading of GAPP array machine code, provides for the debugging and monitoring of GAPP array execution from the host, and implements user-defined instructions.< >
A state-assignment procedure is presented that uses only abstract complexity criteria and produces assignments that are not targeted toward particular implementations. It produces networks similar in complexity to tho...
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A state-assignment procedure is presented that uses only abstract complexity criteria and produces assignments that are not targeted toward particular implementations. It produces networks similar in complexity to those obtained by contemporary methods but is an order of magnitude faster, because it does not use computationally expensive logic synthesis algorithms to predict the effect of assignment on synthesis. Assignments for finite-state machines typically took about 10 minutes on a VAX 11/780.< >
A CMOS sea of gates with 160 K basic cells for random logic and memories is reported. Because of the unique architecture, the LSI offers flexible configuration of RAMs, ROMs, and PLAs (programmable logic arrays) with ...
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A CMOS sea of gates with 160 K basic cells for random logic and memories is reported. Because of the unique architecture, the LSI offers flexible configuration of RAMs, ROMs, and PLAs (programmable logic arrays) with high density and suitable routing areas for random logic circuits, and results in the utilization of 120 K basic cells. It is fabricated with CMOS 1.0- mu m triple-metal-layer process technology.< >
Two turbojet engine control programs were analyzed for potential parallelism. Both were subjected to global, hierarchical, large-grain data-flow analysis, using internally developed data-flow analysis tools. Execution...
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Two turbojet engine control programs were analyzed for potential parallelism. Both were subjected to global, hierarchical, large-grain data-flow analysis, using internally developed data-flow analysis tools. Execution times of constituent code segments or procedures were determined. Data dependences were combined with execution times to determine maximum possible speedup, using the length of the critical path as the shortest execution time. The first control program was divided into 199 code segments, and had a maximum speedup of 7.2. The second program consisted of 64 basic control procedures; this program has a maximum possible speedup of 5.3. The amount of data passed between the dependent tasks was small, averaging 1.3 values per dependency. Static, nonpreemptive schedules have been determined using a heuristic algorithm based on the critical path method. For the first control program this allowed a speedup of 6.6 using 7 processors; for the second, the maximum possible speedup of 5.3 was achieved using 6 processors. The first program is being implemented on a shared-memory bus-shaped multiprocessor.< >
Uses of implied network values or conditions in the context of multilevel logic synthesis are presented. The use of these implications has resulted in performance-enhanced versions, ESPRESSOMLT2 and MLTAUT2, of the tw...
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Uses of implied network values or conditions in the context of multilevel logic synthesis are presented. The use of these implications has resulted in performance-enhanced versions, ESPRESSOMLT2 and MLTAUT2, of the two cornerstone tools of the BOLD system, ESPRESSOMLT (multilevel logic minimizer based on tautology checking) and MLTAUT (multilevel logic verifier). The relationship between the implied values and the intermediate don't care set is presented. Then it is shown how this relationship can be exploited to reduce the number of tautology calls and the number of leaves in the binary recursion tree of tautology checking. A parallelized version MLTAUT2P, which runs on a Sun 3/75 LAN, is discussed. ESPRESSOMLT2, is expected to have speedups of up to a factor of 20 and the parallelized version a factor of over 100.< >
Factoring is a technique for converting a two-level circuit description to a logical equivalent multilevel form to achieve economy or to meet fan-in and fan-out limitations of the given technology. The authors describ...
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Factoring is a technique for converting a two-level circuit description to a logical equivalent multilevel form to achieve economy or to meet fan-in and fan-out limitations of the given technology. The authors describe efficient algorithms that transform a two-level programmable-logic-array (PLA)-like representation of a logic function into a globally optimized multilevel multiple-output switching circuit by the use of algebraic factoring. They present the results of two synthesis algorithms, which show the influence of the factoring strategy on the area and delay of the resulting circuit. The algorithms are part of the CAD system FIGARO, which supports the automatic logic and physical design of finite state machines.< >
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