Small N + -P + spacings have been realised using twin retrograde well technology in combination with an advanced isolation scheme. In this paper suppression of field transistor leakage currents is demonstrated by sim...
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Small N + -P + spacings have been realised using twin retrograde well technology in combination with an advanced isolation scheme. In this paper suppression of field transistor leakage currents is demonstrated by simulation and experimental results. The results show that an N + -P + spacing of 2.5 μm can be realised without increased narrow-width effects in adjacent transistors.
Two turbojet engine control programs were analyzed for potential parallelism. Both were subjected to global, hierarchical, large-grain data-flow analysis, using internally developed data-flow analysis tools. Execution...
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Two turbojet engine control programs were analyzed for potential parallelism. Both were subjected to global, hierarchical, large-grain data-flow analysis, using internally developed data-flow analysis tools. Execution times of constituent code segments or procedures were determined. Data dependences were combined with execution times to determine maximum possible speedup, using the length of the critical path as the shortest execution time. The first control program was divided into 199 code segments, and had a maximum speedup of 7.2. The second program consisted of 64 basic control procedures; this program has a maximum possible speedup of 5.3. The amount of data passed between the dependent tasks was small, averaging 1.3 values per dependency. Static, nonpreemptive schedules have been determined using a heuristic algorithm based on the critical path method. For the first control program this allowed a speedup of 6.6 using 7 processors; for the second, the maximum possible speedup of 5.3 was achieved using 6 processors. The first program is being implemented on a shared-memory bus-shaped multiprocessor.< >
The problem of configurating multiple scan paths in a VLSI circuit is discussed. Based on the analysis of the circuit, certain specific subcircuits are identified and a scan path is next configured for testing each su...
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The problem of configurating multiple scan paths in a VLSI circuit is discussed. Based on the analysis of the circuit, certain specific subcircuits are identified and a scan path is next configured for testing each such subcircuit. Rather than the algorithmic approach, a knowledge-based system strategy has been adopted to automate the approach taken by a human designer to tackle the problem.< >
A static CMOS programmable-logic-array (PLA) architecture has been developed that enables the realization of high-speed control circuits while at the same time providing the low static power consumption inherent in CM...
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A static CMOS programmable-logic-array (PLA) architecture has been developed that enables the realization of high-speed control circuits while at the same time providing the low static power consumption inherent in CMOS technology. The PLA uses a novel circuit configuration and a two-phase clock to latch data between the AND and the OR planes. An 8-input, 13-output, 42-minterm finite state machine has been realized using an automatic generating system, in an area of 0.36 mm/sup 2/. This structure operates from near DC to above 80 MHz.< >
An efficient PLA crosspoint fault simulation algorithm is presented. Parallel Boolean vector operations on a bitwise representation of PLA faults replace set operations, leading to increasing efficiency as the PLA siz...
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An efficient PLA crosspoint fault simulation algorithm is presented. Parallel Boolean vector operations on a bitwise representation of PLA faults replace set operations, leading to increasing efficiency as the PLA size grows. Experimental results demonstrate execution times averaging over 100% faster than PLATYPUS and almost two and a half orders of magnitude faster than the CHIEFS fault simulator.< >
The impact that very large-scale integration (VLSI) has had on engineering education and the acceptance of computer-aided design (CAD) tools for education are considered. Design automation algorithms for CAD tools are...
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The impact that very large-scale integration (VLSI) has had on engineering education and the acceptance of computer-aided design (CAD) tools for education are considered. Design automation algorithms for CAD tools are noted. The effects on university-industry relations are mentioned.< >
Use of high energy ion implantation for retrograde wells requires thick resist layers to prevent implant penetration. Shadowing of the n-well implant results in a displacement in the position of the n-well edge, depen...
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Use of high energy ion implantation for retrograde wells requires thick resist layers to prevent implant penetration. Shadowing of the n-well implant results in a displacement in the position of the n-well edge, dependent on the position across the wafer and implant angle, thereby requiring a larger minimum design rule. Electrical measurement of n + /n-well field transistors as a function of spacing and orientation has been used to investigate the amount of shadowing which occurs for nominal 7° implants. Shadowing effects were found to vary from 0.15 to 0.25μm across a typical 4 inch diameter wafer.
programmable-logic-array (PLA) optimization can be achieved by using heuristic two-level switching-function minimization algorithms. The authors introduce a novel approach to the heuristic-switching-function minimizat...
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programmable-logic-array (PLA) optimization can be achieved by using heuristic two-level switching-function minimization algorithms. The authors introduce a novel approach to the heuristic-switching-function minimization, formulating the problem as a state-space search. Several heuristic evaluation functions are used to guide the search, which is realized by constructing a binary decision tree.< >
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