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检索条件"主题词=Programmable Logic Arrays"

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Non-disjoint decomposition of Boolean functions and its application in FPGA-oriented technology mapping

Non-disjoint decomposition of Boolean functions and its appl...

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EUROMICRO Conference

作者： M. Rawski L. Jozwiak M. Nowicka T. Luba Institute of Telecommunications Warsaw University of Technology Warsaw Poland Section of Digital Information Systems Eindhovan University of Technology Eindhoven Netherlands

We present a new theory of non-disjoint serial decomposition. We also present our new decomposition tool DEMAIN. The decomposition approach implemented in DEMAIN relies on: a partition-based representation of Boolean functions; and an effective balanced decomposition strategy that switches between the parallel and non-disjoint serial decomposition. In consequence, we applied the non-disjoint serial decomposition and parallel decomposition for efficient synthesis of FPGA-based circuits directed towards area or delay optimisation.

关键词： Boolean functions Input variables Field programmable gate arrays Paper technology Circuit synthesis Delay Switches logic circuits programmable logic arrays Table lookup

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FPGA technology mapping optimization by rewiring algorithms

FPGA technology mapping optimization by rewiring algorithms

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Wai-Chung Tang Wing-Hang Lo Yu-Liang Wu Shih-Chieh Chang Department of Computer Science and Engineering Chinese University of Hong Kong Sha Tin Hong Kong China Department of Computer Science and Information Engineering National Chung Cheng University Chiayi Taiwan

ISBN: (纸本)0780388348

Rewiring algorithms provide a new style of logic transformations by replacing a target wire with its alternative wire while maintaining the functionality of the circuit. In this paper, these algorithms are used to minimize the number of LUTs used to map a given circuit with Flowmap. The proposed approach is to evaluate each alternative wire with Flowmap and choose the first one which can reduce the number of LUTs by 1 or more. Despite its simplicity, it can efficiently transform the circuit to one suitable to be mapped with Flowmap and used in FPGA. Experimental result shows that the proposed approach can reduce up to 17% of the LUTs in a circuit without any depth increment.

关键词： Field programmable gate arrays Wire Table lookup Partitioning algorithms Space technology logic circuits Computer science programmable logic arrays programmable logic devices Boolean functions

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Using CORBA as a distributed extension solution for OSGi

Using CORBA as a distributed extension solution for OSGi

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IEEE Workshop on Electronics, Computer and Applications (IWECA)

作者： Yuanli Wu Jun Jia Hong Wang Information Dept PLA Beijing China Academy of Millitary Science Beijing China

ISBN: (纸本)9781479945641

To meet the requirements of OSGi distributed processing capabilities from enterprise computing, this paper proposes a convenient way which adds distributed computing capability to OSGi framework and supports interoperation between OSGi and legacy CORBA applications. This is achieved by using CORBA dynamic technology which implements the remote service invocation capability and CORBA naming service which supports remote service discovery capability. In the end, this paper proves the distributed processing capabilities by testing our implementation in a simple scenario with a legacy CORBA application.

关键词： programmable logic arrays Java Presses

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An Automatic Rectilinear Partitioning Procedure for Standard Cells

An Automatic Rectilinear Partitioning Procedure for Standard...

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Design Automation Conference

作者： Mely Chen Chi AT and T Bell Laboratories Murray Hill NJ USA

This paper describes a new approach to automatically partition and place the standard cells in a rectilinear area on a chip among the pre-placed macro cells (RAM, ROM, PLA etc.) and I/O pads. The macro cells may be placed anywhere on the chip. The topological and physical constraints, and the net list connectivity are accounted for simultaneously. This procedure has been implemented in the AT&T Bell Laboratories LTX2 chip layout system.

关键词： Read only memory Permission programmable logic arrays Design automation Standards publication Geometry Integrated circuit technology Integrated circuit interconnections Partitioning algorithms Distributed computing

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Thermal Sensor Allocation and Placement for Reconfigurable Systems 06

Thermal Sensor Allocation and Placement for Reconfigurable S...

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IEEE International Conference on Computer-Aided Design

作者： Rajarshi Mukherjee Somsubhra Mondal Seda Ogrenci Memik Synopsys Inc. Mountain View CA Department of Electrical Engineering and Computer Science Northwestern University Evanston IL USA

ISBN: (纸本)9781595933898

Temperature monitoring using thermal sensors is an essential tool for evaluating the thermal behavior and sustaining the reliable operation in high-performance and high-power systems. With current technology scaling and integration trends timely and accurate detection of localized heating will be evermore important. In this work, we address the creation of a resource efficient sensor infrastructure for computing systems that are of regular nature, such as logic array-based computing platforms. We propose algorithms to embed thermal sensors into a regular structure to minimize the number of sensors and determine sensor locations required to maintain a given accuracy in temperature sensing for a given design. Our algorithms are tailored for minimal usage of thermal sensors to suit a variety of architectural conditions. For programmable logic arrays the highly application-specific usage of the hardware resources leads to unpredictable thermal profiles. As a result, post-manufacture instantiation of thermal sensors is desired, which in turn demands the use of native hardware resources, which can be scarce. We demonstrate that using our techniques the number of sensors required to monitor a set of hotspots is reduced by 75% on an average, across different sizes of logic arrays for different hotspot distributions compared to a uniform distribution of sensors throughout the fabrics

关键词： Sensor systems Thermal sensors Temperature sensors Sensor arrays logic arrays programmable logic arrays Hardware Temperature measurement Heating Algorithm design and analysis

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A 5.1 ns, 5000 gate, CMOS PLD with selectable frequency multiplication and in-system programmability

A 5.1 ns, 5000 gate, CMOS PLD with selectable frequency mult...

引用

Custom Integrated Circuits Conference (CICC)

作者： J. Costello J. Balicki V. Bocchino M. Chan K. Nishiwaki B. Nouban N. Tran B. Vest M. Wong Altera Corporation San Jose CA USA

A high density programmable logic device (PLD) specifically developed for high performance and for ease of use in production flows is presented. This device is designed on a 0.5 /spl mu/m triple layer metal process to produce a 55 kmil/sup 2/ die size and with the built-in frequency multiplier, allows system performance of up to 140 MHz to be achieved.

关键词： Frequency conversion Clocks Pins Macrocell networks programmable logic devices logic devices programmable logic arrays Testing Costs Voltage

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Temporal floorplanning using 3D-subTCG

Temporal floorplanning using 3D-subTCG

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Asia and South Pacific Design Automation Conference

作者： Ping-Hung Yuh Chia-Lin Yang Yao-Wen Chang Hsin-Lung Chen Department of Computer Science and Information Engineering National Taiwan Normal University Taipei Taiwan Graduate Institute of Electronics Engineering & Department of Electrical Engineering National Taiwan Normal University Taipei Taiwan Etron Technology Inc. Hsinchu Taiwan

ISBN: (纸本)0780381750

Improving logic capacity by time-sharing. dynamically reconfigurable FFGAs are employed to handle designs of high complexity and functionality. In this paper, we use a novel topological floorplan representation, named 3D-subTCC (?-Dimensional sub-Transitive Closure Graph) to deal with the 3-dimensional (temporal) floorplanninglplacement problem. arising from dynamically reconfigurable FPGAs. The 3D-subTCG uses three transitive closure graphs to model the temporal and spatial relations between modules. We derive the feasibility conditions for the precedence constraints induced by the execution of the dynamically reconfigurable FPGAs. Because the geometric relationship is transparent to 3D-subTCG and its induced operations, we can easily detect any violation of temporal precedence constraints on 3D-aubTCG. We also derive imponant properties of the 3D-subTCG to reduce the solution space and shorten the running time for 3D (temporal) fwrplanninglplacement. Experimental results show that our 3D-subTCG based algorithm is very effective and efficient.

关键词： Reconfigurable logic Field programmable gate arrays programmable logic arrays Computer science logic design Time sharing computer systems Read-write memory logic devices Flip-flops Hardware

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Design of discrete event control systems for programmable logic controllers using T-Timed Petri nets

Design of discrete event control systems for programmable lo...

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IEEE International Symposium on Computer Aided Control System Design (CACSD)

作者： A.H. Jones M. Uzam N. Ajlouni Research Institute for Design Manufacture and Marketing Intelligent Machinery Division University of Sanford Salford UK

As automated manufacturing systems become more complex, the need for an effective design tool to produce both a high level discrete event control system (DECS) and a low level ladder logic implementation, becomes increasingly more important. Petri nets represent the most effective method for the design of such DECSs. The conversion of such Petri net controllers into ladder logic has been greatly simplified through the advent of the token passing logic methodology. The new technique provides a straightforward but powerful method by which to implement ladder logic code. In this paper the fundamental T-Timed Petri net structures and their associated ladder logic equivalents are described. Finally, the design of a DECS for a manufacturing system is considered. A heuristic Petri net controller is developed for the manufacturing system, and then the methodology is used to derived structured ladder logic code.

关键词： Control systems logic design programmable logic arrays programmable logic devices programmable control Petri nets logic programming Industrial control Automatic control Counting circuits

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Ultrasound contrast agents targeted to malignancies: optimizing cellular attachment

Ultrasound contrast agents targeted to malignancies: optimiz...

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Annual Northeast Bioengineering Conference

作者： K. Oum J. Vega L. Leodore F. Forsberg J.B. Liu D. Merton M.A. Wheatley School of Biomedical Engineering Science and Health Systems Drexel University Philadelphia PA USA Department of Radiology Drexel University Philadelphia PA USA Department of Chemical Engineering Drexel University Philadelphia PA USA

Hollow poly (lactic acid) (PLA) microcapsules were modified with Arg-Gly-Asp (RGD) peptide to create a targeted contrast agent (CA) that enhances ultrasound imaging. The RGD peptide targets cell-surface receptors (integrins /spl alpha//sub v//spl beta//sub 3/ and /spl alpha//sub v//spl beta//sub 5/) which are overexpressed in cancer and angiogenesis. The influence of RGD surface density and RGD spacer length were evaluated for their contribution to CA attachment to human breast cancer cells. The CA performance was dependent on both the RGD surface density and glycine spacer length and therefore should be considered in the design of a site-targeted CA. The optimized RGD peptide modified microcapsules are ideal candidates for targeted diagnostic imaging and for drug delivery.

关键词： Ultrasonic imaging Peptides Humans Breast cancer programmable logic arrays Sequences Adhesives Cells (biology) Biomedical engineering Chemical engineering

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Research and Implementation of Component Candidate Set Based on Reconfiguration Router Unit

Research and Implementation of Component Candidate Set Based...

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International Conference on Computational Intelligence and Software Engineering (CiSE)

作者： Qiang Liu Binqiang Wang Nan Jiang Xiaoya Han

As a result of the research and design of reconfiguration router unit (RRU), the producing of network equipment is turned into component composition as building block. Based on the component composition and the character of RRU, this paper proposes the concept-CCS (component candidate set). The scheme of creating component candidate set is based on the BP neural network. The CSS is proposed to resolve the problem of automation and dynamic in the process of RRU component composition. According to the CCS model, this paper describes the running state of component, self-determination running and adaptive evolution operation. Simulation experiment showed that this CCS-based method is precious and effective.

关键词： Manufacturing Neural networks Computer architecture Vocabulary Switching systems programmable logic arrays Logistics Cascading style sheets Automation Carbon capture and storage

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