A 2500-gate programmablelogic device with a 25-ns typical propagation delay is described. This CMOS EPROM device has less than 50-mW power dissipation. Its simple, regular architecture is supported by industry-standa...
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A 2500-gate programmablelogic device with a 25-ns typical propagation delay is described. This CMOS EPROM device has less than 50-mW power dissipation. Its simple, regular architecture is supported by industry-standard third-party software tools. Global routing and subdivisable macrocells provide gate utilization factors equivalent to gate arrays.< >
A tool is described for constructing the connectivity between components given a state graph into which the components are to be mapped. Examples taken from previous papers in the field are used to demonstrate this co...
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A tool is described for constructing the connectivity between components given a state graph into which the components are to be mapped. Examples taken from previous papers in the field are used to demonstrate this connectivity binder. The results point to heuristics that are used to generate solutions to the problem. Questions addressed include how much of the state graph must be considered at one time to give reasonable results and how the search space can be prune to achieve good solutions quicker. The code for this project is written in C and runs under 4.2 BSD Unix.< >
A structured design procedure for systems integration sequential logic which is to be implemented on programmablelogic controllers is presented. The procedure offers the advantages of producing intrinsically robust s...
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A structured design procedure for systems integration sequential logic which is to be implemented on programmablelogic controllers is presented. The procedure offers the advantages of producing intrinsically robust software which is very easy to understand and to modify as systems requirements change. The approach takes advantage of the sequential nature nature of processors to assure that the order of solution of the sequential logic equations is consistent with maximum speed and instantaneous correctness of the output states. The authors present examples of the basic elements of the structured design procedure from which any type of system integration can be implemented. An example is given of an industrial die cast molding machine system.< >
An automatic tool that heuristically determines a good partitioning of a single large programmablelogic array (PLA) into a PLA with a smaller number of encoded outputs (and usually fewer product terms), followed by a...
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An automatic tool that heuristically determines a good partitioning of a single large programmablelogic array (PLA) into a PLA with a smaller number of encoded outputs (and usually fewer product terms), followed by a set of decoders to regenerate the original outputs, has been developed. Initial results using logic descriptions of processor chips and a benchmark set of industrial PLAs show area savings of up to 35% and delay reductions of up to 45%. The approach can be considered an alternative to Boolean decomposition and factoring in multilevel logic synthesis.< >
Multiple-valued Boolean minimization is proposed as a technique for identifying and extracting good Boolean factors which can be used as strong divisors to minimize the literal count and the area of a multilevel logic...
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Multiple-valued Boolean minimization is proposed as a technique for identifying and extracting good Boolean factors which can be used as strong divisors to minimize the literal count and the area of a multilevel logic network. Given a two-level logic function, a subset of inputs to the function is selected such that the number of good Boolean factors contained in this subset of inputs is large. If the targeted implementation is a set of interconnected PLAs, the different cube combinations given by the subset of inputs are re-encoded to reduce the number of product terms in the logic function. A novel algorithm for the re-encoding is given that is based on the notion of partial satisfaction of constraints. Algorithms have been developed that identify a set of factors which maximally decrease the literal count of the logic network when they are used as strong divisors. Results obtained on several benchmark examples that illustrate the efficacy of the techniques are presented.< >
Until recently, the problem of path planning for a robot arm operating among unknown obstacles has been treated on a case-by-case basis with different algorithms for different arm kinematics. A unified theoretical fra...
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Until recently, the problem of path planning for a robot arm operating among unknown obstacles has been treated on a case-by-case basis with different algorithms for different arm kinematics. A unified theoretical framework is presented in this paper, which allows one to use one scheme for any of the many possible configurations of simple arm manipulators with revolute and prismatic (sliding) joints.
The use of compilers for structured cells such as RAMs, ROMs, multipliers and PLAs (programmable logic arrays) has become widespread in the design of application-specific integrated circuits (ASICs). The authors prese...
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The use of compilers for structured cells such as RAMs, ROMs, multipliers and PLAs (programmable logic arrays) has become widespread in the design of application-specific integrated circuits (ASICs). The authors present a methodology for testing circuits made from these compiled cells. The key elements of this methodology are the vector compilers that generate test suites for the compiled cells and an isolation strategy that allows these test suites to be applied to embedded functional blocks.< >
A method for PLA (programmablelogic-array) test-pattern generation based on a branch-and-bound algorithm that function monotonicity is presented. The algorithm makes irrevocable input assignments first, resulting in ...
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A method for PLA (programmablelogic-array) test-pattern generation based on a branch-and-bound algorithm that function monotonicity is presented. The algorithm makes irrevocable input assignments first, resulting in the efficient generation of compact test sets. In most cases there is no backtracking. An intelligent branching heuristic is presented. The algorithm handles extended fault models, including cross-point and delay faults. Heuristics which speed up test-set generation and improve test-set compaction are discussed. Results of tests on a wide range of benchmark PLAs are included.< >
Current techniques in logic/fault simulation treat the problem as a nonnumeric one in which the basic primitives involved are Boolean operations, string matching/manipulation operations, bitwise or wordwise comparison...
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Current techniques in logic/fault simulation treat the problem as a nonnumeric one in which the basic primitives involved are Boolean operations, string matching/manipulation operations, bitwise or wordwise comparison operations, etc. A technique for reformulating the problem in terms of standard vector and matrix operation primitives which are well supported on all scientific machines is described. The overall computing environment is assumed to be a scientific/engineering one, with Fortran as the primary coding medium and the hardware biased toward numerically intensive applications. Attention is restricted to VLSI array logic.< >
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