A declaration hierarchical notation is introduced that allows the parametric representation of entire families of VLSI circuits. Layout, schematic diagrams and network structure are all accommodated by the notation in...
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A declaration hierarchical notation is introduced that allows the parametric representation of entire families of VLSI circuits. Layout, schematic diagrams and network structure are all accommodated by the notation in a way that emphasizes common elements. The notation is the basic of a structured environment for developing design generators as well as capturing design expertise.< >
A two-chip digital TV with the potential for 650 horizontal lines of resolution and implemented with 195 K transistors has been described. Both are fabricated in 1.5-/spl mu/m double-metal CMOS technology and assemble...
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A two-chip digital TV with the potential for 650 horizontal lines of resolution and implemented with 195 K transistors has been described. Both are fabricated in 1.5-/spl mu/m double-metal CMOS technology and assembled in plastic packages. The video processor with a 2 H one-transistor cell dynamic RAM line memory contains 140 K transistors in a 62-mm/SUP 2/ chip, operates up to 50 MHz, and dissipates 250 mW at 14.3 MHz. The synchronous processor dissipates 110 mW at 14.3 MHz.
Two strategies for encoding the inputs and outputs of highly structured logicarrays (HSLAs) are introduced. The two schemes are particularly relevant for concurrent error detection of both permanent and nonpermanent ...
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Two strategies for encoding the inputs and outputs of highly structured logicarrays (HSLAs) are introduced. The two schemes are particularly relevant for concurrent error detection of both permanent and nonpermanent errors in programmable logic arrays (PLAs) and read-only memories (ROMs). The first method of concurrent error detection (CED) is based on a comprehensive fault model and relies on detection of unidirection errors. The second approach relies on a detailed examined of decoder layouts resulting in fault avoidance through layout rules, which avoid failures causing unidirectional errors. Efficient parity techniques are shown to provide a low-overhead solution to concurrent error detection when coupled with appropriate fault-avoidance techniques.
The testing properties of inverter-free PLAs make them ideal for application to totally self-checking and easily testablecircuits. After a class of test patterns and masking relations for these new patterns are determ...
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The testing properties of inverter-free PLAs make them ideal for application to totally self-checking and easily testablecircuits. After a class of test patterns and masking relations for these new patterns are determined, a complete test setfor single and multiple crosspoint faults can be easily generated. Moreover, the procedure does not require any fault *** code space inputs detect all single and multiple faults in PLAs for totally self-checking circuits, even if the faultsare not unidirectional. The test results can be used to analyze easily testable PLAs. With minor hardware changes in one-inputdecoder PLAs, the personality matrix will serve as a complete test set.
A 6 K-gate GaAs gate array has been successfully designed and fabricated using a novel large-noise-margin Schottky-diode level-shifter capacitor-coupled FET logic (SLCF) circuitry and a WN/SUB x/ gate selfaligned ligh...
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A 6 K-gate GaAs gate array has been successfully designed and fabricated using a novel large-noise-margin Schottky-diode level-shifter capacitor-coupled FET logic (SLCF) circuitry and a WN/SUB x/ gate selfaligned lightly doped drain (LDD) structure GaAs MESFET process. Chip size was 8.0/spl times/8.0 mm/SUP 2/. A basic cell can be programmed as an SLCF inverter, a two-input NOR, or a two-input NAND gate. The unloaded propagation delay time was 76 ps/gate a 1.2-mW/gate power dissipation. The increases in delay time due to various loading capacitances were 10 ps/fan-in, 45 ps/fan-out, and 0.64 ps/IF. A 16-b serial-to-parallel-to-serial (S/P/S) data-conversion circuit was constructed on the gate array as an application example. A maximum operation frequency of 852 MHz was achieved at a 952-mW power dissipation, including I/O buffers.
A simulated-annealing programmable-logic array (PLA) folding algorithm is presented for simple as well as multiple-column folding. Experimental results indicate that the algorithm performs very well. In many test prob...
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A simulated-annealing programmable-logic array (PLA) folding algorithm is presented for simple as well as multiple-column folding. Experimental results indicate that the algorithm performs very well. In many test problems, the results are superior to those produced by the well-known heuristic algorithm of G. De Micheli and A. Sangiovanni-Vincentelli (1983). It is also shown that the algorithm can be extended to handle constrained folding.
A CAMAC data scanner was designed and manufactured. The scanner is in conformance with LeCroy's 4290 series DATABUS interface. The scanner supports CAMAC single action and block transfer mode with zero suppress ca...
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A CAMAC data scanner was designed and manufactured. The scanner is in conformance with LeCroy's 4290 series DATABUS interface. The scanner supports CAMAC single action and block transfer mode with zero suppress capability. The S2 timing of CAMAC cycle may be skipped to squeeze data acquisition cycle. The scanners are located at front-end CAMAC crates in the FASTBUS based TOPAZ data acquisition system.
ASIC design methodologies are assessed from the system designer's point of view by comparing the entire IC-related product cost, design schedule, functionality, and risks to that of designs containing standard dev...
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ASIC design methodologies are assessed from the system designer's point of view by comparing the entire IC-related product cost, design schedule, functionality, and risks to that of designs containing standard devices. ASIC methodologies include programmablelogic devices, gate arrays, standard cells, and full custom, all primarily in 2-m CMOS, at production volumes of 1 to 100K units per year and at complexities of 5OO to 20 000 gates per device. It is shown that "gates per pin" is the key determinant of total IC-related cost. Products containing ASIC cost less than those containing SSI/MSI, since ASICs raise the number of gates per pin from 2 to a range of 40-200. More surprising, products using ASIC devices cost less than products containing combinations of standard LSI/VLSI and SSI/MSI, if their gates per pin is 2-3 times that of the products containing standard devices. Each design methodology has regions, or market segments, where it is competitive. But there are large regions of small cost differences between two ASIC methodologies. Currently, these regions use primarily the older methodologies, i.e., gate arrays at low production volumes and full custom at high volumes. They also provide future opportunities for standard cells. Currently, IC manufacturing cost accounts for about 15 percent of the logic-related total cost, field maintenance for 17 percent, device and system development for 11 percent, and systems related manufacturing cost for 57 percent. These percentages are expected to migrate to 17, 20, 13, and 50 percent, respectively, by 1990. Our ASIC techno-economic assessment is summarized in 27 nomograms, figures, and charts.
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