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检索条件"主题词=Programmable Logic Arrays"
4439 条 记 录,以下是4061-4070 订阅
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A notation for describing multiple views of VLSI circuits
A notation for describing multiple views of VLSI circuits
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Design Automation Conference
作者: J.-L. Baer M.-C. Liem L. McMurchie R. Nottrott L. Snyder W. Winder NW Laboratory for Integrated Systems Department of Computer Science University of Washington Seattle WA USA
A declaration hierarchical notation is introduced that allows the parametric representation of entire families of VLSI circuits. Layout, schematic diagrams and network structure are all accommodated by the notation in... 详细信息
来源: 评论
Comments on "Detection of Faults in programmable logic arrays"
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IEEE Transactions on Computers 1986年 第10期C-35卷 930-931页
作者: Liang Ye-Wei Jin Wei Beijing Institute of Computer Technology Beijing China
This correspondence shows two counter examples which contradict the Theorems 4 and 5 in [1].
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A CMOS CHIP PAIR FOR DIGITAL TV
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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1987年 第5期22卷 835-840页
作者: SUZUKI, S KAWAI, K MURAMATSU, K TOSHIBA CORP AUDIO VIDEO PROD ENGN LABISOGU KUYOKOHAMAJAPAN
A two-chip digital TV with the potential for 650 horizontal lines of resolution and implemented with 195 K transistors has been described. Both are fabricated in 1.5-/spl mu/m double-metal CMOS technology and assemble... 详细信息
来源: 评论
CONCURRENT ERROR-DETECTION IN HIGHLY STRUCTURED logic-arrays
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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1987年 第4期22卷 583-594页
作者: FUCHS, WK CHEN, CYR ABRAHAM, JA Computer Systems Group Coordinated Science Laboratory University of Illinois Urbana IL USA
Two strategies for encoding the inputs and outputs of highly structured logic arrays (HSLAs) are introduced. The two schemes are particularly relevant for concurrent error detection of both permanent and nonpermanent ... 详细信息
来源: 评论
TESTING AND APPLICATIONS OF INVERTER-FREE PLAS
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IEEE DESIGN & TEST OF COMPUTERS 1987年 第6期4卷 30-40页
作者: RAJSKI, J AGARWAL, VK McGill University
The testing properties of inverter-free PLAs make them ideal for application to totally self-checking and easily testablecircuits. After a class of test patterns and masking relations for these new patterns are determ... 详细信息
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A 6K-GATE GAAS GATE ARRAY WITH A NEW LARGE-NOISE-MARGIN SLCF CIRCUIT
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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1987年 第5期22卷 755-761页
作者: TERADA, T IKAWA, Y KAMEYAMA, A KAWAKYU, K SASAKI, T KITAURA, Y ISHIDA, K NISHIHORI, K TOYODA, N VLSI Research Center Toshiba Corporation Kawasaki Japan
A 6 K-gate GaAs gate array has been successfully designed and fabricated using a novel large-noise-margin Schottky-diode level-shifter capacitor-coupled FET logic (SLCF) circuitry and a WN/SUB x/ gate selfaligned ligh... 详细信息
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SYSTEM ARCHITECTURE OF A GALLIUM-ARSENIDE ONE-GIGAHERTZ DIGITAL IC TESTER
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COMPUTER 1987年 第5期20卷 58-70页
作者: FOUTS, DJ JOHNSON, JM BUTNER, SE LONG, SI UNIV CALIF SANTA BARBARA DEPT ELECT & COMP ENGNSANTA BARBARACA 93106
First Page of the Article
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PLA FOLDING BY SIMULATED ANNEALING
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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1987年 第2期22卷 208-215页
作者: WONG, DF LEONG, HW LIU, CL Department of Computer Science University of Illinois Urbana-Champaign Urbana IL USA
A simulated-annealing programmable-logic array (PLA) folding algorithm is presented for simple as well as multiple-column folding. Experimental results indicate that the algorithm performs very well. In many test prob... 详细信息
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CAMAC DATA SCANNER WITH LRS4299 DATABUS INTERFACE
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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 1987年 第4期34卷 954-957页
作者: IKEDA, H National Laboratory for High Energy Physics (KEK) Tsukuba Ibaraki Japan
A CAMAC data scanner was designed and manufactured. The scanner is in conformance with LeCroy's 4290 series DATABUS interface. The scanner supports CAMAC single action and block transfer mode with zero suppress ca... 详细信息
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A TECHNOECONOMIC ASSESSMENT OF APPLICATION-SPECIFIC INTEGRATED-CIRCUITS - CURRENT STATUS AND FUTURE-TRENDS
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PROCEEDINGS OF THE IEEE 1987年 第6期75卷 829-841页
作者: FEY, CF PARASKEVOPOULOS, DE XEROX CORP XEROX MICROELECTR CTRREG LSI DESIGN CTREL SEGUNDOCA 90245
ASIC design methodologies are assessed from the system designer's point of view by comparing the entire IC-related product cost, design schedule, functionality, and risks to that of designs containing standard dev... 详细信息
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