A complex design effort, the 80386 was nevertheless one of the company's most successful projects. The work was completedin less time than scheduled and set an Intel record for tapeout to mask fabricator. The stra...
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A complex design effort, the 80386 was nevertheless one of the company's most successful projects. The work was completedin less time than scheduled and set an Intel record for tapeout to mask fabricator. The strategy incorporated both top-downand bottom-up design approaches. The top-down flow was external architectural definition, internal architecture, internalunit RTL (register transfer logic) and finally detailed logic. The bottom-up flow was detailed transistor and cell circuitdesign and layout, block (ALU, PLA, etc.) circuit design and layout, and finally global circuit design and layout. Testabilityalso played an important part in the design's success. The 80386 combines two forms of designed-in test functions: built-inself-test and test hooks or functions explicitly designed in to aid testing.
The design is presented, in which a conventional PLA is modified by adding redundancy circuits. Three types of fault can be repaired: crosspoint, bridging, and stuck-at faults.
The design is presented, in which a conventional PLA is modified by adding redundancy circuits. Three types of fault can be repaired: crosspoint, bridging, and stuck-at faults.
A device independent Fastbus coupler interface has been designed which is capable of high speed operation as Fastbus master, data space slave, and limited control space slave. The design has been implemented on two di...
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A device independent Fastbus coupler interface has been designed which is capable of high speed operation as Fastbus master, data space slave, and limited control space slave. The design has been implemented on two different but plug compatible boards, one using TTL programmablelogic and featuring average latency of 185 nanoseconds and capable of cycle times of 200 nanoseconds, and the other using ECL macrocell arrays and featuring average latency of 35 nanoseconds and capable of cycle times of this order. Use of these boards in both unintelligent and intelligent Fastbus host interfaces as well as self contained Fastbus processing modules is described. This work has been and is being supported by the U. S. Department of Energy under SBIR contracts DE-ACO1-83ER80078, DE-ACO2-85ER80273, and DE-ACO2-87ER80455, and by the New York State Science and Technology Foundation under contract SBIR (86)-58.
A double word-line memory ROM (DWM-ROM) for use in gate arrays is described. It allows for an automatic layout by reducing the input pin count in the word lines by using two-step addressing. The advantage of this meth...
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A double word-line memory ROM (DWM-ROM) for use in gate arrays is described. It allows for an automatic layout by reducing the input pin count in the word lines by using two-step addressing. The advantage of this method has been verified by implementing a 16-bit microprocessor using an 8 K-gate array, based on a gate-isolated cell configuration, employing 1.5-/spl mu/m double-metal CMOS technology. The 16-bit /spl times/ 64-word ROM in the processor saves 30% of the transistor area due to the DWM-ROM.
A VME/VMX bus interface has been designed and built to interface a VME-based data acquisition system to CAMAC. The interface communicates via a differential bus with a companion unit that functions as a CAMAC crate co...
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A VME/VMX bus interface has been designed and built to interface a VME-based data acquisition system to CAMAC. The interface communicates via a differential bus with a companion unit that functions as a CAMAC crate controller. The interface maps both VMiE and VMX address cycles into appropriate CAMAC cycles. Special diagnostic features have been incorporated in the design to allow quick fault detection and location.
In the synthesis of digital circuits, one encounters the problem of identifying blocks which have been designed, so that there is no replication in the expensive effort of generating the physical layout of these block...
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In the synthesis of digital circuits, one encounters the problem of identifying blocks which have been designed, so that there is no replication in the expensive effort of generating the physical layout of these blocks. We present a model for the synthesis of combinational logic into complex MOS circuits and present a ranking and unranking procedure to characterize the layout of each complex MOS circuit.
MIS is both an interactive and a batch-oriented multilevel logic synthesis and minimization system. MIS starts from the combinational logic extracted, typically, from a high-level description of a macrocell. It produc...
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MIS is both an interactive and a batch-oriented multilevel logic synthesis and minimization system. MIS starts from the combinational logic extracted, typically, from a high-level description of a macrocell. It produces a multilevel set of optimized logic equations preserving the input-output behavior. The system includes both fast and slower (but more optimal) versions of algorithms for minimizing the area, and global timing optimization algorithms to meet system-level timing constraints. This paper provides an overview of the system and a description of the algorithms used. Included are some examples illustrating an input language used for specifying logic and don't-cares. Parts on an industrial chip have been re-synthesized using MIS with favorable results as compared to equivalent manual designs.
A DPCM (differential pulse-code modulation) coder integrated in a 2-/spl mu/m CMOS technology is discussed. The motivation was to introduce low-cost coders for video signals compatible with the planned European ISDN. ...
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A DPCM (differential pulse-code modulation) coder integrated in a 2-/spl mu/m CMOS technology is discussed. The motivation was to introduce low-cost coders for video signals compatible with the planned European ISDN. Due to the internal feedback loop, the main problem was to achieve the required operating speed of 13.5 MHz sampling rate. Measurements of fabricated samples proved that the expected performance was achieved.
A VME-resident Camac crate controller is described which maps all Camac functions into the address space of a 68000 microprocessor. The controller also contains a VME bus requester, thus allowing it to contribute Cama...
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A VME-resident Camac crate controller is described which maps all Camac functions into the address space of a 68000 microprocessor. The controller also contains a VME bus requester, thus allowing it to contribute Camac data, completely formatted, to a global event buffer.
A DRAM controller which handles up to 128 1-Mb DRAM chips has been developed based on the WE 32100 32-bit microsystem. Fabricated with a 1.5 /spl mu/m twin-tub CMOS technology, nominal DRC devices operate at an intern...
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A DRAM controller which handles up to 128 1-Mb DRAM chips has been developed based on the WE 32100 32-bit microsystem. Fabricated with a 1.5 /spl mu/m twin-tub CMOS technology, nominal DRC devices operate at an internal clock rate of 36 MHz. High circuit speed was achieved by the use of clock-skew minimization techniques to limit clock signal variations to within 3.0 ns throughout the chip, and a modified standard-cell approach called gate-matrix custom cells. The chip implementation process was completed in less than four months and error-free silicon was obtained from the first mask set.
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