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检索条件"主题词=Programmable Logic Arrays"
4439 条 记 录,以下是4071-4080 订阅
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DESIGN AND TEST OF THE 80386
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IEEE DESIGN & TEST OF COMPUTERS 1987年 第3期4卷 42-50页
作者: GELSINGER, PP Intel Corp.
A complex design effort, the 80386 was nevertheless one of the company's most successful projects. The work was completedin less time than scheduled and set an Intel record for tapeout to mask fabricator. The stra... 详细信息
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ON THE DESIGN OF A REDUNDANT programmable logic ARRAY (RPLA)
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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1987年 第1期22卷 114-117页
作者: WEY, CL VAI, MK LOMBARDI, F UNIV COLORADO DEPT ELECT & COMP ENGNBOULDERCO 80309
The design is presented, in which a conventional PLA is modified by adding redundancy circuits. Three types of fault can be repaired: crosspoint, bridging, and stuck-at faults.
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UNIVERSAL FASTBUS INTERFACE BOARDS AND ASSOCIATED MODULES
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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 1987年 第4期34卷 786-789页
作者: SISKIND, EJ NYCB Real Time Computing Inc.orporated Lattingtown NY USA
A device independent Fastbus coupler interface has been designed which is capable of high speed operation as Fastbus master, data space slave, and limited control space slave. The design has been implemented on two di... 详细信息
来源: 评论
A CONFIGURABLE ROM CIRCUIT FOR USE IN GATE arrays
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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1987年 第1期22卷 117-118页
作者: UEDA, M SAKASHITA, K ARAKAWA, T OKAZAKI, K ASAI, S KURAMITSU, Y LSI Research and Development Laboratory Mitsubishi Electric Corporation Limited Itami Hyogo Japan
A double word-line memory ROM (DWM-ROM) for use in gate arrays is described. It allows for an automatic layout by reducing the input pin count in the word lines by using two-step addressing. The advantage of this meth... 详细信息
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A VME/VMX - CAMAC INTERFACE AND CRATE CONTROLLER
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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 1987年 第4期34卷 751-755页
作者: MCPARLAND, C BIESER, F Lawrence Berkeley National Laboratory Berkeley CA USA
A VME/VMX bus interface has been designed and built to interface a VME-based data acquisition system to CAMAC. The interface communicates via a differential bus with a companion unit that functions as a CAMAC crate co... 详细信息
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A RANKING ALGORITHM FOR MOS CIRCUIT LAYOUTS
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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1987年 第1期6卷 17-21页
作者: NEFF, CA NAIR, R IBM Thomas J. Watson Research Center Yorktown Heights NY USA
In the synthesis of digital circuits, one encounters the problem of identifying blocks which have been designed, so that there is no replication in the expensive effort of generating the physical layout of these block... 详细信息
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MIS - A MULTIPLE-LEVEL logic OPTIMIZATION SYSTEM
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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1987年 第6期6卷 1062-1081页
作者: BRAYTON, RK RUDELL, R SANGIOVANNIVINCENTELLI, A WANG, AR Department of Electrical Engineering and Computer Sciences University of California Berkeley CA USA
MIS is both an interactive and a batch-oriented multilevel logic synthesis and minimization system. MIS starts from the combinational logic extracted, typically, from a high-level description of a macrocell. It produc... 详细信息
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REALIZATION OF A DPCM CODER FOR 13.5-MHZ SAMPLING RATE IN CMOS TECHNOLOGY
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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1987年 第6期22卷 1196-1197页
作者: ROTHERMEL, A Fraunhofer Institute of Microelectronic Circuits and System Duisburg Germany
A DPCM (differential pulse-code modulation) coder integrated in a 2-/spl mu/m CMOS technology is discussed. The motivation was to introduce low-cost coders for video signals compatible with the planned European ISDN. ... 详细信息
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AN INTELLIGENT VME-BASED CAMAC CRATE CONTROLLER
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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 1987年 第4期34卷 1033-1035页
作者: SCHEETZ, RA LEVINE, MJ Physics Department Brockhaven National Laboratory Upton NY USA
A VME-resident Camac crate controller is described which maps all Camac functions into the address space of a 68000 microprocessor. The controller also contains a VME bus requester, thus allowing it to contribute Cama... 详细信息
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A CMOS DRAM-CONTROLLER CHIP IMPLEMENTATION
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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1987年 第3期22卷 491-494页
作者: POON, TC KERESTES, M FISCHER, RF SAMPSON, GP HWANG, SJ YANG, WJ WILLIS, ML AT&T BELL LABS MURRAY HILLNJ 07974
A DRAM controller which handles up to 128 1-Mb DRAM chips has been developed based on the WE 32100 32-bit microsystem. Fabricated with a 1.5 /spl mu/m twin-tub CMOS technology, nominal DRC devices operate at an intern... 详细信息
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