Modern programmablelogic devices have capabilities that are well suited for them to assume a central role in the holistic implementation of networked systems. We have devised a highly flexible soft platform architect...
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Modern programmablelogic devices have capabilities that are well suited for them to assume a central role in the holistic implementation of networked systems. We have devised a highly flexible soft platform architecture abstracted from such physical devices, which may be viewed as a particularly configurable and programmable type of network processor. In this paper, we discuss a programming model for the architecture, and present an XML-based description language for expressing the programming information. This intermediate language is designed both to be an attractive compilation target for domain-specific languages used for describing networking applications, and also to have efficient mappings to programmablelogic devices, harnessing to the full their high degree of concurrency, interconnectivity and programmability. We present a detailed example, where a high-speed remote procedure call (RPC) protocol server for gigabit Ethernet was described directly in the XML-based language, and automatically compiled to a working implementation on a platform FPGA device. The exercise was carried out by a non-hardware expert in only two weeks, thus demonstrating the unlocking of access to programmablelogic technology.
Structural health monitoring is an area of growing interest and is worthy of new and innovative approaches. Since the automatic diagnosis of structures is very complex and challenging, recent research to apply deep le...
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Structural health monitoring is an area of growing interest and is worthy of new and innovative approaches. Since the automatic diagnosis of structures is very complex and challenging, recent research to apply deep learning techniques has been actively conducted. In this study, we assumed that a PLA beam copied by 3D printing is the smallest unit constituting a complex structure and applied GRU to detect defects. To set the defect point of the beam, a total of four holes were drilled at regular intervals, and then a mass was attached. Signals at different locations were collected through a vibrator and trained through GRU, and the results were compared in terms of RMSE value. As a result of this experiment, we checked the defect by inputting test data into the trained model and were able to measure the defect degree of the PLA beam with a weighted average F1 score of 84%.
For a specific domain of operation (e.g., public key cryptography), it is possible to provide the required level of algorithm agility by using a limited amount of reconfigurability which avoids the overhead associated...
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ISBN:
(纸本)0780366085
For a specific domain of operation (e.g., public key cryptography), it is possible to provide the required level of algorithm agility by using a limited amount of reconfigurability which avoids the overhead associated with generic programmablelogic. The resulting Domain Specific Reconfigurable Cryptographic Processor (DSRCP) represents a prototype implementation for the domain of public key cryptography. The processor ISA is based upon the recently adopted IEEE 1363-2000 Public Key Cryptography Standard. The DSRCP is the first reported hardware-based solution that performs conventional arithmetic, modular integer arithmetic, binary Galois Field arithmetic (i.e., GF(2/sup /spl alpha//)), and elliptic curve arithmetic over GF(2/sup /spl alpha//). In addition, it does so in an energy efficient manner.
With the rapid decrease in device dimensions and the resulting density and performance inprovements, designers can include significant amounts of memory within a logic circuit. Conventional memories have absorbed spec...
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With the rapid decrease in device dimensions and the resulting density and performance inprovements, designers can include significant amounts of memory within a logic circuit. Conventional memories have absorbed specialized logic functions to satisfy system design requirements. Video DRAMs, multiported and embedded SRAMs, digital TV CCDs and encryption EPROMs are current examples of devices exploring this avenue. Not all ventures are likely to succeed. The panel will address issues which will influence this success or failure, Not only will implementation aspects be probed, but panelists will attempt to contrast cost effectiveness of approaches, current and future market directions, testability concerns, and the future systems potential of application specific memories.
A CML programmablelogic array customized by an automated laser system will be discussed. Up to 2252 aluminum links are vaporized to obtain the desired pattern. Access time is typically 4ns. Added circuitry allows 100...
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A CML programmablelogic array customized by an automated laser system will be discussed. Up to 2252 aluminum links are vaporized to obtain the desired pattern. Access time is typically 4ns. Added circuitry allows 100% test coverage of all "stuck-at" faults in the unprogrammed state.
The introduction of multiplexer based FPGAs has renewed interest in logic design using multiplexers. This paper presents an iterative approach for the synthesis of combinational circuits using a tree network of 2-to-1...
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The introduction of multiplexer based FPGAs has renewed interest in logic design using multiplexers. This paper presents an iterative approach for the synthesis of combinational circuits using a tree network of 2-to-1 multiplexers. A characterizing parameter of Boolean functions, known as Ratio Parameters, has been used in each iteration to reduce the search space. The obtained multiplexer network is then mapped onto the Actel ACT1 FPGA basic blocks. The performance of the proposed approach has been evaluated by comparing the results of 11 MCNC benchmark problems with the results of the existing technology mappers.
Dedicated systems with hardware and software tailored for the application provide tremendous performance improvements over systems based on general-purpose hardware. The authors describe SIERA, a system being develope...
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Dedicated systems with hardware and software tailored for the application provide tremendous performance improvements over systems based on general-purpose hardware. The authors describe SIERA, a system being developed for rapid-prototyping of the hardware and software components of such dedicated real-time systems starting from a high-level description. Based on their experience of automated generation at the chip level which they developed with the LAGER system, they identify two distinct phases in the design process. The first is the process of mapping the high-level system specification to a set of interacting hardware and software modules. The second is the generation of these software and hardware modules. A mix of mapping, synthesis and library based techniques is being utilized to accomplish these tasks.< >
Four spatial/spectral imaging diagnostics show relativistic self-channeling of a 25 TW, 1 ps laser pulse limited only by the length of the gas-jet target. Collective scattering of a probe beam provides a spectrally-re...
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Four spatial/spectral imaging diagnostics show relativistic self-channeling of a 25 TW, 1 ps laser pulse limited only by the length of the gas-jet target. Collective scattering of a probe beam provides a spectrally-resolved image of large-amplitude plasma waves indicating an intensity >10/sup 18/ W/cm/sup 2/ at 4 mm from the laser focus.
In article, it is stated principles of creation of programmed logical integrated circuits and digital signal processing methods. Are resulted on a specific example process of formation code sequence the meaning code o...
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ISBN:
(数字)9781728125640
ISBN:
(纸本)9781728125657
In article, it is stated principles of creation of programmed logical integrated circuits and digital signal processing methods. Are resulted on a specific example process of formation code sequence the meaning code of required station in signal transmission devices in fiber optical systems.
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