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检索条件"主题词=Programmable Logic Arrays"
4442 条 记 录,以下是4101-4110 订阅
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The Cerenkov free-electron laser
The Cerenkov free-electron laser
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International Electron Devices Meeting (IEDM)
作者: J. Walsh C. Shaughnessy R. Layman G. Dattoli G.-P. Gallerano A. Renieri Dartmouth College Hanover NH USA ENEA Frascati Italy
来源: 评论
A CMOS 32b microprocessor with on-chip cache and transmission lookahead buffer
A CMOS 32b microprocessor with on-chip cache and transmissio...
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IEEE International Conference on Solid-State Circuits (ISSCC)
作者: H. Kadota J. Miyake I. Okabayashi T. Maeda T. Okamoto Y. Takagi K. Kagawa E. Ichinohe Matsushita Semiconductor Research Center Osaka Japan
THIS PAPER WILL DESCRIBE a single chip CMOS 32b micro-processor supporting a smart memory hierarchy with on chip Cache and TLB (Transmission Lookaside Buffer(.
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Design of a Process Tolerant Cell Library for Regular Structures using Symbolic Layout and Hierarchical Compaction
Design of a Process Tolerant Cell Library for Regular Struct...
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European Conference on Solid-State Circuits (ESSCIRC)
作者: L. Rijnders P. Six H. De Man IMEC Heverlee Belgium Professor at Katholieke Universiteit Leuven
A method is presented to design cell libraries, using a symbolic layout editor and a hierarchical compaction algorithm with automatic terminal fitting. In contrast to language based procedural layout, this technique g... 详细信息
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A Design Rule Independent Cell Compiler
A Design Rule Independent Cell Compiler
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Design Automation Conference
作者: J.S.J. Chen D.Y. Chen Integrated Corrputer Aided Design Inc. Sunnyvale CA USA
To achieve fast turn around, appropriate performance and efficient silicon area in ASIC design, it is desirable to have the capability of generating new customized cells overnight. A design rule independent cell compi... 详细信息
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Fast, Small, and Static Combinatorial CMOS Circuits
Fast, Small, and Static Combinatorial CMOS Circuits
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Design Automation Conference
作者: B.P. Serlet Xerox PARC Computer Science Laboratory Palo Alto CA USA
We present ALPS, a new way to generate layout from boolean equations. We use an original tree-structured representation of arbitrary boolean expressions, more compact than classic disjunctive form, allowing fast symbo... 详细信息
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Array Optimization for VLSI Synthesis
Array Optimization for VLSI Synthesis
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Design Automation Conference
作者: D.F. Wong C.L. Liu Department of Computer Science University of Illinois Urbana-Champaign Urbana IL USA
We present in this paper an algorithm that solves a general array optimization problem. The algorithm can be used for compacting Gate Matrix layouts, SLA's, Weinberger arrays, and for multiple folding of PLA's... 详细信息
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The MAP Pilot Project at IBM Endicott
The MAP Pilot Project at IBM Endicott
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IEEE Technical Conference on Southern Tier
作者: E. Wagner IBM Endicott USA
Endicott's Manufacturing Automation Protocol (MAP) pilot project demonstrates to the industry that IBM is seriously interested in MAP. Two software products, MAP Communication Server (MCS) and MAP Application Serv... 详细信息
来源: 评论
A 25NS CMOS Electrically Erasable FPLA
A 25NS CMOS Electrically Erasable FPLA
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Symposium on VLSI Circuits
作者: S. M. Jimmy Lee Ali Pourkeramati International CMOS Technology 2031 Concourse Drive San Jose CA
Recently, several CMOS PLDs were reported using nonvolatile memory technologies for array implementation. However, the architecture of these CMOS PLDs are limited in only one programmable array feeding into a group of... 详细信息
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A Parallel PLA Minimization Program
A Parallel PLA Minimization Program
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Design Automation Conference
作者: R. Galivanche S.M. Reddy Motorola Inc. Chandler AZ USA Department of Electrical & Computer Engineering University of Iowa Iowa IA USA
In this paper we report on an implementation of a parallel algorithm to minimize PLA realizations of logic functions. The algorithm is derived from a widely available PLA minimization program called ESPRESSO-MV. The p... 详细信息
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The SYCO Control Section Compiler
The SYCO Control Section Compiler
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European Conference on Solid-State Circuits (ESSCIRC)
作者: N. Mhaya A.A. Jerraya TIM3-INPG/IMAG laboratory Grenoble France
This paper describes the SYCO Control Section Compiler (CPC). The SYCO silicon compiler generates microprocessor-like circuits. Each circuit is constitueted of a data path (DP) and a control section (CS) which is a st... 详细信息
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