THIS PAPER WILL DESCRIBE a single chip CMOS 32b micro-processor supporting a smart memory hierarchy with on chip Cache and TLB (Transmission Lookaside Buffer(.
THIS PAPER WILL DESCRIBE a single chip CMOS 32b micro-processor supporting a smart memory hierarchy with on chip Cache and TLB (Transmission Lookaside Buffer(.
A method is presented to design cell libraries, using a symbolic layout editor and a hierarchical compaction algorithm with automatic terminal fitting. In contrast to language based procedural layout, this technique g...
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A method is presented to design cell libraries, using a symbolic layout editor and a hierarchical compaction algorithm with automatic terminal fitting. In contrast to language based procedural layout, this technique guarantees correctness and easy updatability to new circuit techniques and layout rules. It can be applied to all regular hierarchical layout structures where constrained cells have to be designed. Once the library is established it can be used over and over again with different personality matrices for fast generation of correct layout.
To achieve fast turn around, appropriate performance and efficient silicon area in ASIC design, it is desirable to have the capability of generating new customized cells overnight. A design rule independent cell compi...
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To achieve fast turn around, appropriate performance and efficient silicon area in ASIC design, it is desirable to have the capability of generating new customized cells overnight. A design rule independent cell compiler which is capable of generating nearly optimal layout and all the desirable user interfaces such as automatic place and route database, data sheet, SPICE information and the layout verification model for any user specified cell is reported in this paper. The algorithms used for cell synthesis are also discussed in this paper.
We present ALPS, a new way to generate layout from boolean equations. We use an original tree-structured representation of arbitrary boolean expressions, more compact than classic disjunctive form, allowing fast symbo...
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We present ALPS, a new way to generate layout from boolean equations. We use an original tree-structured representation of arbitrary boolean expressions, more compact than classic disjunctive form, allowing fast symbolic manipulation and natural mapping onto silicon. This implementation of ALPS produces static CMOS layout using a cascode-switch style. We present measurements done on fabricated circuits. For a large class of functions, particularly semi-regular control logic, VLSI layout generated by ALPS compares favorably in speed and area to PLAS and Standard-Cell designs.
We present in this paper an algorithm that solves a general array optimization problem. The algorithm can be used for compacting Gate Matrix layouts, SLA's, Weinberger arrays, and for multiple folding of PLA's...
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We present in this paper an algorithm that solves a general array optimization problem. The algorithm can be used for compacting Gate Matrix layouts, SLA's, Weinberger arrays, and for multiple folding of PLA's. Our approach is based on the technique of simulated annealing. A major contribution of this paper is the formulation of the solution space which facilitates an effective search for an optimal solution. Experimental results are very encouraging.
Endicott's Manufacturing Automation Protocol (MAP) pilot project demonstrates to the industry that IBM is seriously interested in MAP. Two software products, MAP Communication Server (MCS) and MAP Application Serv...
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Endicott's Manufacturing Automation Protocol (MAP) pilot project demonstrates to the industry that IBM is seriously interested in MAP. Two software products, MAP Communication Server (MCS) and MAP Application Server (MAS), were developed in IBM Palo Alto, California, and demonstrated at the November 1985 Autofact show. In Endicott, IBM Series/1's (S/1) monitor various processes, used in the manufacturing of advanced circuit panels (ACP). Ultimately, MAP will significantly reduce the time required to develop software that will connect the programmablelogic controllers (PLC) on the manufacturing floor and the IBM S/1's used to monitor the processes. A significant portion of the cost associated with new PLC installations is directly related to software. This cost will essentially be eliminated because MAP provides a standard interface. MAP will allow programmablelogic controllers to communicate with each other and other computers directly, without requiring additional software. A broadband cable was installed in November of 1985, allowing both MAP and IBM PC Network to operate on the same physical cable. The MAP network connects the Series 1's on the manufacturing floor, while PC Network links IBM PC's between.
Recently, several CMOS PLDs were reported using nonvolatile memory technologies for array implementation. However, the architecture of these CMOS PLDs are limited in only one programmable array feeding into a group of...
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Recently, several CMOS PLDs were reported using nonvolatile memory technologies for array implementation. However, the architecture of these CMOS PLDs are limited in only one programmable array feeding into a group of fixed OR gates. Therefore, the efficiency of its logic integration is greatly limited due to lack of product term sharing capability. This paper will describe a 25ns, 50mA CMOS programmable Electrically Erasable logic Device with both reconfigurable AND array and OR array. High speed is achieved by separating logic path from program/verify circuit, and a bootstrapped single-ended sense amplifier.
In this paper we report on an implementation of a parallel algorithm to minimize PLA realizations of logic functions. The algorithm is derived from a widely available PLA minimization program called ESPRESSO-MV. The p...
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In this paper we report on an implementation of a parallel algorithm to minimize PLA realizations of logic functions. The algorithm is derived from a widely available PLA minimization program called ESPRESSO-MV. The parallel algorithm was implemented on a shared memory multicomputer system. In the course of development of the parallel algorithm, some changes were made to ESPRESSO-MV which resulted in lower computing time. Experimental results using 105 PLAs are included.
This paper describes the SYCO Control Section Compiler (CPC). The SYCO silicon compiler generates microprocessor-like circuits. Each circuit is constitueted of a data path (DP) and a control section (CS) which is a st...
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This paper describes the SYCO Control Section Compiler (CPC). The SYCO silicon compiler generates microprocessor-like circuits. Each circuit is constitueted of a data path (DP) and a control section (CS) which is a stack of control slices. The SYCO system makes use of the CPC to produce the control section from a high level description. CPC handles an hierarchical control section and involves efficient optimization mechanism. The present version of the CPC generates each control slice using a PLA. The compilation of the algorithmic description of each control slice is composed of three steps: the state table generation, the logic optimization and the PLA generation. CPC is available, the paper indicates the results of the 6502 control section compilation.
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