In this paper we present the ALGIC silicon compiler system. Starting from a structural and functional description of digital VLSI circuits, the system generates automatically the corresponding layout in a full custom ...
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In this paper we present the ALGIC silicon compiler system. Starting from a structural and functional description of digital VLSI circuits, the system generates automatically the corresponding layout in a full custom design style. Main components of the ALGIC system are a system monitor module, a parameterisable macrocell generator, an appropriate floorplanner with 100% routing solution including planar VDD/GND trees and a block-oriented timing verifier. One essential feature of the system is the high degree of integration between all program modules using the concept of abstract data types. The flexibility and performance of the whole system is demonstrated by real design examples in the field of DSP applications.
Algorithms for model reference adaptive control were developed in recent years, and their stability and convergence properties have been investigated. Typical algorithms in continuous time involve strictly positive re...
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Algorithms for model reference adaptive control were developed in recent years, and their stability and convergence properties have been investigated. Typical algorithms in continuous time involve strictly positive real conditions on the reference model, while similar discrete time algorithms do not require such conditions. We show how algorithms differ by the use of an input error versus an output error, and present a continuous time input error adaptive control algorithm which does not involve SPR conditions. The connections with other schemes are discussed. The input error scheme has general stability and convergence properties that are similar to the output error scheme. However, analysis using averaging methods reveals some preferable convergence properties of the input error scheme. Several other advantages are also discussed.
This paper introduces a standard structure for VLSI design which we call the mesh array and describes a design tool called logicIAN which minimizes a set of functions for realization in CMOS mesh arrays. logicIAN feat...
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This paper introduces a standard structure for VLSI design which we call the mesh array and describes a design tool called logicIAN which minimizes a set of functions for realization in CMOS mesh arrays. logicIAN features multi-level logic synthesis through recursive enumeration of each function. Several techniques to speed-up the minimization process in logicIAN are described.
This paper describes a new approach to automatically partition and place the standard cells in a rectilinear area on a chip among the pre-placed macro cells (RAM, ROM, PLA etc.) and I/O pads. The macro cells may be pl...
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This paper describes a new approach to automatically partition and place the standard cells in a rectilinear area on a chip among the pre-placed macro cells (RAM, ROM, PLA etc.) and I/O pads. The macro cells may be placed anywhere on the chip. The topological and physical constraints, and the net list connectivity are accounted for simultaneously. This procedure has been implemented in the AT&T Bell Laboratories LTX2 chip layout system.
This paper describes VTIstate, VLSI Technology's state machine compiler. The compiler derives combinational logic and registers to make a state machine, and synthesizes the combinational logic with three optimizat...
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This paper describes VTIstate, VLSI Technology's state machine compiler. The compiler derives combinational logic and registers to make a state machine, and synthesizes the combinational logic with three optimization steps. The 1986 Design Automation conference synthesis benchmark set is used to compare the results with previously reported logic synthesis programs.
The interaction between a user and instrumentation can be represented by a standard notation or grammar. The software tools necessary generate computational structures called parsers. The parsers described in the pape...
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The interaction between a user and instrumentation can be represented by a standard notation or grammar. The software tools necessary generate computational structures called parsers. The parsers described in the paper are implemented in hardware using programmable logic arrays which are realized as v. l. s. i. silicon devices.
A global floorplanning approach is presented which allows designers to quickly explore layout issues during the initial stages of the IC design process. The approach is based on a combined mincut and slicing paradigm,...
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A global floorplanning approach is presented which allows designers to quickly explore layout issues during the initial stages of the IC design process. The approach is based on a combined mincut and slicing paradigm, in an effort to ensure routability. A slicing-tree representation is employed, upon which efficient traversal operations are applied resulting in area-efficient floorplans. The method allows modules to be specified as having a number of possible dimensions, and considers I/O pads as well as layout constraints. As a global improvement over previous floorplanning efforts, an in-place partitioning scheme is applied in conjunction with a combined exhaustive and heuristic bipartitioning approach. Moreover, a global channel routing and module I/O pin assignment scheme is used for floorplan evaluation, whereby module dimensions are chosen in conjunction with routing area, ensuring compact floorplans. A computer program, Mason, is presented which efficiently implements the approach and provides an interactive environment for designers to perform floorplanning. The performance of the program is discussed in terms of several industrial examples.
Current understanding of the PLA folding problem is limited to simple empirical evidence from studies of heuristic methods. This paper presents a theoretical approach through an analytical and statistical analysis. Th...
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Current understanding of the PLA folding problem is limited to simple empirical evidence from studies of heuristic methods. This paper presents a theoretical approach through an analytical and statistical analysis. The problem is first mapped into a set theoretic model. Using a random selection heuristic as a basis, a probability density function (PDF) is derived for the expected number of folds under a set of simplifying assumptions. This PDF is derived in terms of the three fundamental properties of a PLA, r the number of rows, c the number of columns, and d the density. Empirical results obtained from folding thousands of randomly generated PLA's verify the accuracy of the derived probability density function. A technique is developed whereby the PDF can also be used to predict the size of optimal folding sets. A new folding heuristic is introduced which is shown to perform better than other heuristic algorithms in the literature, when applied to a set of randomly generated PLA's. This is the first folding heuristic to have an analytical basis for its expected results, as derived from the PDF function.
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