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检索条件"主题词=Programmable Logic Arrays"

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A programmable true piecewise approximation logarithmic amplifier

A programmable true piecewise approximation logarithmic ampl...

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International Conference on Microelectronics, ICM

作者： Mostafa Shaterian Adib Abrishamifar Hossein Shamsi Department of Electrical and Electronic Engineering K N Toosi University of Technology Tehran Iran Department of Electrical and Electronic Engineering Iran University of Science and Technology Tehran Iran

This paper describes the operation theory, mathematical analysis and simulation of parallel summation type of the true piecewise approximation logarithmic amplifiers. It also reports a programmable logarithmic amplifier to have a desired logarithmic characteristic in special applications. To design the programmable structure, mathematical analysis of parallel summation type of the true piecewise approximation logarithmic amplifier is performed and based on it, a new method for improving its characteristic and some methods for adding flexibility and programmability to the structure is described. The presented programmable logarithmic architecture can be used in applications with variant and uncertain input signal range such as wide range wireless receivers and radar applications and some analog signal processing applications.

关键词： Circuits Dynamic range Piecewise linear approximation Operational amplifiers Paper technology Mathematical analysis Radar applications programmable logic arrays Piecewise linear techniques Low-noise amplifiers

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FPGA implementation of a deterministic bit-stream neuron

FPGA implementation of a deterministic bit-stream neuron

引用

International Conference on Semiconductor

作者： I. Bostan V. Ionescu C. Moldovan Electronics Department University of Piteşti Pitesti Romania National Institute for R and D in Microtechnologies Bucharest Romania

This paper presents a digital hardware implementation of a deterministic Bit-Stream Artificial Neuron (AN) with ten inputs. The design was made to be implemented in a FPGA device for a minimal hardware requirement. The simulation for XCV3200 Virtex FPGA device, showed the possibility to place around 200 neurons (including the extra logic required to run the networks). As each neuron has ten connections this means that it will be possible to place a network with 2000 weights.

关键词： Field programmable gate arrays Neurons Artificial neural networks Stochastic processes Neural network hardware programmable logic arrays Object oriented modeling logic devices Application software logic design

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A correctness proof of the SRP protocol

A correctness proof of the SRP protocol

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Huabing Yang Xingyuan Zhang Yuanyuan Wang People''s Liberation Army University of Science and Technology China

The correctness of a routing protocol can be divided into two parts, a liveness property proof and a safety property proof. The former requires that route(s) should be discovered and data be transmitted successfully, while the latter requires that the discovered routes have some desired characters such as containing only benign nodes. While safety properties are relatively easier to prove, the proof of liveness properties is usually harder. This paper presented a liveness proof of a secure routing protocol, SRP (P. Papadimitratos and Z. J. Haas, 2002) in Isabelle/HOL (T. Nipkow et al., 2002). The liveness property proved says that if a data package needs to be sent, then it will be sent and then received, and finally, the sender will receive an acknowledgement sent back by the receiver. There are three main contributions in this paper. Firstly, a liveness property is proved for a secure routing protocol, and this has never been done before. Secondly, our validation model can deal with arbitrarily many nodes including malicious ones, and nodes are allowed to move randomly. Thirdly, a fail set is defined to restrict the attackers' actions, so that the safety properties used to prove the liveness property can be established. The paper explains why it is reasonable to prevent malicious nodes from performing the events in fail set.

关键词： Routing protocols Safety Ad hoc networks Packaging Communication system security programmable logic arrays Wireless application protocol Mobile computing Computer networks Wireless communication

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Synthesis challenges for next-generation high-performance and high-density PLDs

Synthesis challenges for next-generation high-performance an...

引用

Asia and South Pacific Design Automation Conference

作者： J. Gong Songjie Xu Dept. of Comput. Sci. California Univ. Los Angeles CA USA Aplus Design Technologies Inc. Los Angeles CA USA

Rapid evolution of programmable logic device (PLD) architectures and the increasingly demanding requirements to meet with high-density and high-performance PLD designs call for a new generation of PLD synthesis tools to support many important capabilities not available in the existing synthesis tools. In this paper, we analyze the synthesis challenges and opportunities in supporting next-generation high-performance and high-density PLDs. We classify these challenges into two categories: (i) those implied from the advance of PLD architectures, including synthesis for hierarchical architectures and synthesis for heterogeneous architectures, and (ii) those driven by the requirements for high-density and high-performance PLD designs, including layout-driven synthesis, incremental synthesis, and IF-based synthesis. We shall discuss existing and/or potential solutions to these problems and outline research opportunities and directions for the development of next-generation PLD synthesis systems.

关键词： programmable logic arrays logic devices Integrated circuit synthesis programmable logic devices Large scale integration Electronics industry Lead compounds Macrocell networks Read-write memory Table lookup

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Systematic comparison of various kinds of higher order vector elements for triangles

Systematic comparison of various kinds of higher order vecto...

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Asia-Pacific Conference on Environmental Electromagnetics (CEEM)

作者： Wen-lu Yin Cong Deng Da Peng Shun-lian Chai Jun-jie Mao College of Electronics Science and Engineering National University of Defense Technology Changsha China

In this paper, the characteristic and performance of different kinds of 2D triangular interpolatory vector elements are compared systematically and explicitly. Nedelec's functional spaces and Nedelec constraints are discussed, and some important properties of various vector elements are analyzed. The performance of different vector elements is then compared through numerical examples.

关键词： Finite difference methods Sparse matrices Time domain analysis Polynomials Maxwell equations Matrix decomposition Transmission line matrix methods EMP radiation effects Laboratories programmable logic arrays

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Scaffolding Instruction Design Research Based on Zone of Proximal Development of Learning Community

Scaffolding Instruction Design Research Based on Zone of Pro...

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International Conference of Educational Innovation through Technology (EITT)

作者： Suojuan Zhang Wenqian Lai Jinyu Song Xiaohan Yu Xianglin Liao Jiandong Hao College of Command & Control Engineering Army Engineering University of PLA Nanjing China School of Education Science Nanjing Normal University Nanjing China

ISBN: (纸本)9781538696040;9781538696033

The Zone of Proximal Development holds that instruction and development are processes that influence and depend on each other, emphasizing the development differences between different individuals. This study takes full consideration of ZPD among the learning individuals with diversification and overlapping, which innovatively construct a learning community based on the ZPD of learning community. On this basis, the scaffolding instructional pattern is introduced to design practical activities, which provides research ideas and design approaches for practical teaching activities, and finally forms operational teaching cases and application demonstration.

关键词： Education Databases Control engineering programmable logic arrays Task analysis Technological innovation Psychology

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Initial Evidence for Understanding the Relationship between Product Line Architecture and Software Architecture Recovery

Initial Evidence for Understanding the Relationship between ...

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Brazilian Symposium on Software Components, Architectures and Reuse (SBCARS)

作者： Crescencio Rodrigues Lima Neto Mateus Passos Soares Cardoso Christina Von Flach Garcia Chavez Eduardo Santana De Almeida Federal Institute for Education Science and Technology of Bahia (IFBA) Federal University of Bahia (DCC/UFBA)

Context: Over the years, the interest on software architecture recovery has increased. Due to software product line inherent complexity, the recovery of product line architecture is crucial to alleviate difficulties and enable benefits during the SPL development. Objective: In order to gather data and evidence about the relationship between product line architecture and software architecture recovery, (Method:) we performed a literature survey using some steps of systematic literature review method and an exploratory study. Results: We identified the appearance of more elaborated studies over the years and the majority of solution proposals are used to recover the architecture from legacy systems source code to provide the SPL reference architecture. Conclusion: Most of the studies presented solution proposal combined with case studies. But, only a few of them address empirical evaluation. With the software architecture recovery evolution, more research combining recovery of product line architecture and empirical evaluation still necessary.

关键词： Computer architecture Software architecture programmable logic arrays Proposals Market research Data mining Software product lines

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Fine grain parallelism on a MIMD machine using FPGAs

Fine grain parallelism on a MIMD machine using FPGAs

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IEEE Workshop on FPGAs for Custom Computing Machines

作者： F. Raimbault D. Lavenier S. Rubini B. Pottier Campus de Beaulieu Irisa Rennes France Département d'Informatique Université de Bretagne Occidentale Brest France

The article presents the use of an FPGA chip (Xilinx 3090) to set up a fast systolic communication agent on a linear asynchronous network of transputer processors; the machine is called ArMen. The authors' work relies on the systolic programming environment ReLaCS, a close cousin to the C programming language. ReLaCS provides synchronous communication operators to simplify the programming of data transfers that occur in systolic algorithms. The ReLaCS compiler generates C programs that perform the computation process and the data management process of a systolic network.< >

关键词： Field programmable gate arrays Parallel processing programmable logic arrays programmable logic devices Program processors Writing logic arrays Registers Parallel architectures Buildings

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A system for heuristic modifications on PLA-specifications

A system for heuristic modifications on PLA-specifications

引用

EUROMICRO Conference

作者： R. Rauscher A. Krause Department of Computer Science University of Hamburg Hamburg Germany Multimedia-PC Product Development Philips Semiconductors (PCALE) Hamburg Germany

When specifying a PLA for the implementation of a numerical function, usually an adhoc procedure is followed: Generating real values, some type of scaling, rounding to integers, and finally binary coding. Examining the numerical exactness of the performed steps in detail, some kind of blurring can always be recognized. In fact, designers have to accept such unavoidable effects. In many practical applications a good compromise can be achieved between a reasonable decrease of PLA costs and art acceptable amount of implicated deviation. We introduce in this paper the optimization tool HOPE which includes the described heuristics. It is applicable in any design procedure which needs PLAs and uses ESPRESSO as an integral part.

关键词： programmable logic arrays Costs Energy consumption Electronic design automation and methodology logic design Computer science Product development Read only memory Delay Design optimization

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Digital systems design with ASIC and FPGA: a novel course using CD/DVD and on-line formats

Digital systems design with ASIC and FPGA: a novel course us...

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IEEE International Conference on Microelectronic Systems Education

作者： W. Burleson Sheng Xu Electrical & Computer Engineering University of Massachusetts Amherst MA USA

A new course at the University of Massachusetts Amherst in digital systems design uses a novel approach of comparing ASIC and FPGA technologies, implementations, methodologies, CAD tools and trends. The course builds on basic courses in VLSI, HDL-based design and programmable logic but introduces the design of large-scale systems and the associated methodologies and tools. Recent advancements due to Moore's law have resulted in significant challenges in physical design, including interconnection, power consumption, reliability and verification. These challenges are explored at a fundamental level as well as solutions in modern CAD tools from Cadence, Synopsys, Xilinx and Altera. Both ASIC and FPGA solutions are explored and the economic, performance, power and flexibility tradeoffs are studied for each technology. The course was offered to undergraduates, graduates and engineers in industry through live, CD/DVD and on-line formats. The course is fully archived on CD/DVD and on the Web at: http://***/ece/vspgroup/burleson /courses/559/.

关键词： Digital systems Application specific integrated circuits Field programmable gate arrays DVD Design automation Very large scale integration logic design programmable logic arrays programmable logic devices Large-scale systems

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