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PLATYPUS - A PLA TEST PATTERN GENERATION TOOL

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1986年第4期5卷 633-644页

作者： WEI, RS SANGIOVANNIVINCENTELLI, A Department of Electrical Engineering and Computer Science University of California Berkeley CA USA

PLATypus (PLA Test pattern generation and logic simulation tool) is an efficient tool for large PLA's which is interfaced with other existing PLA tools such as the folding program PLEASURE [12] and the logic minimizer ESPRESSO II-C [11] developed at the University of California at Berkeley. A new algorithm is proposed based on complementation and the tautology check of a logic cover, derived from the PLA personality matrix. Both complementation and tautology check are performed by advanced logic manipulation algorithms used in the logic minimization program ESPRESSO II-C [11]. The algorithm is exact, i.e., every testable crosspoint fault is tested, and maximum fault coverage is guaranteed. A quick preprocess, the biased random test generation, is used followed by the proposed algorithm to achieve the best balance between run time and test-set compactness. The program is refined at various stages by many powerful heuristics in the area of fault processing order, backend fault simulation, "don't-care" bit fixing, and on-the-fly test compaction. Both single stuck-at and crosspoint fault models are supported. PLATYPUS can also be used as a logic simulation tool and redundancy identifier. Test pattern generation has been performed by PLATYPUS on a large number of industrial PLA's.

关键词： programmable logic arrays Test pattern generators logic testing Automatic testing logic arrays Very large scale integration Minimization methods Compaction Power system modeling Redundancy

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APPLICATION OF A MICROPROCESSOR BASED SOLID-STATE programmable logic SYSTEM FOR CONTROL OF CLASS 1E COMPONENTS AND DEVICES

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IEEE TRANSACTIONS ON ENERGY CONVERSION 1986年第2期1卷 30-35页

作者： REBBAPRAGADA, RV HICKS, D GARRITY, GE CRBRP PROJECT OAK RIDGETN 37831 CONSOLIDATED CONTROLS CORP BETHELCT 06801

The paper discusses the microprocessor based Solid State programmable logic System (SSPLS) designed for the Clinch River Breeder Reactor Plant (CRBRP) which was terminated in December 1983 by U.S. Congress. Even though procurement of equipment did not take place, the topics discussed here reflect the advanced engineering and design completion (85 percent) on the project and the authors feel that the information presented reflects worthwhile experience associated with the implementation of the state-of-the-art technology and may benefit future designs as well as the industry in general. Topics presented include discussion on design description and hardware, programming, verification and validation, licensing concerns and requirements on reliability and maintainability. The paper describes licensing interaction with the Nuclear Regulatory Commission (NRC) Staff at the construction permit stage and outlines additional details that would be needed at an operating license permit stage.

关键词： Microprocessors Solid state circuits logic devices programmable logic arrays programmable logic devices programmable control Control systems Licenses logic design Rivers

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A ONE-DAY CHIP - AN INNOVATIVE IC CONSTRUCTION APPROACH USING ELECTRICALLY RECONFIGURABLE logic VLSI WITH ON-CHIP programmable INTERCONNECTIONS

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1986年第2期21卷 223-227页

作者： IKAWA, Y URUI, K WADA, M TAKADA, T KAWAMURA, M MIYATA, M AMANO, N SHIBATA, T TOSHIBA CORP INFORMAT & COMMUN SYST LABKAWASAKI 210JAPAN TOSHIBA CORP DIV SEMICONDKAWASAKI 210JAPAN

A new custom IC design methodology and the associated logic VLSI chip, which offer an ultimately fast turnaround-time logic IC construction method, are proposed. The chip contains various kinds of logic functional blocks, such as inverters, NORs, NANDs, flip-flops, shift registers, counters, adders, multiplexers, and ALUs. Up to 200 SSI/MSI standard logic blocks can be provided. The E/SUP 2/PROM-type MOSFET switch matrix is adjacent to the functional blocks, in order to connect any output to specific inputs of the functional blocks. It also offers a ready-to-test aid, obtained by monitoring the signal waveform developed inside the chip. These features have the advantage over the present custom IC design methods (gate array, standard cell, silicon compiler, programmable logic array) that the designer can easily redesign the logic to obtain a digital system in an IC in a single day.

关键词： Reconfigurable logic Very large scale integration programmable logic arrays logic design Design methodology Switches Digital integrated circuits Pulse inverters Flip-flops Shift registers

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SYNAPSE - AN EXPERT SYSTEM FOR VLSI DESIGN

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COMPUTER 1986年第7期19卷 78-89页

作者： SUBRAHMANYAM, PA AT&T Bell Laboratories

First Page of the Article

关键词： Expert systems Very large scale integration programmable logic arrays logic circuits Equations User interfaces Large scale integration Fabrication Geometry Terminology

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SEMICUSTOM AND CUSTOM LSI TECHNOLOGY

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PROCEEDINGS OF THE IEEE 1986年第12期74卷 1636-1645页

作者： OKUDA, N SUGAI, M GOTO, N Toshiba VLSI Research Center Kawasaki Japan

Semicustom and custom LSIs have become very important for system manufacturers because they provide system products with distinctive features that cannot be furnished by using only standard LSIs such as microprocessors. From this point of view, rapid development is essential for semicustom and custom LSIs, but there are other factors to be considered for determining the device technology and design methodology such as performance requirements, allowable development costs, and production quantities. In this paper, these aspects for semicustom and custom LSI development are discussed. We first review the device technology and then discuss various design methodologies with an emphasis on standard cell designs. New design methodologies, such as silicon compilers and AI approaches, are also included.

关键词： Large scale integration Design methodology Manufacturing Semiconductor device manufacture Standards development Microprocessors Costs logic design Electronics industry programmable logic arrays

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OPTIMIZATION OF ONE-BIT FULL ADDERS EMBEDDED IN REGULAR STRUCTURES

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IEEE TRANSACTIONS ON ACOUSTICS SPEECH AND SIGNAL PROCESSING 1986年第5期34卷 1289-1300页

作者： IWANO, K STEIGLITZ, K Department of Computer Science Princeton University Princeton NJ USA

We study the problem of optimizing the transistor sizes in the one-bit nMOS full adder either isolated or embedded in a regular array. A local optimization method that we call the critical-path optimization method is developed. In this method, two parameters at a time are changed along the critical path until a locally optimal choice of transistor sizes is found. The critical-path optimization method uses the Berkeley VLSI tools and the hierarchical layout language ALLENDE developed at Princeton. First, we optimize the isolated one-bit full adder implemented in three ways: as a PLA, data selector, and with random logic. The details of the critical-path optimization method and power-time tradeoff curves are illustrated here. Second, we optimize the one-bit full adder embedded in a simple array multiplier. The entire 3 × 3, 4 × 4, 8 × 8, and 10 × 10 multipliers are optimized and their local optima are compared. Because the optimization of the entire circuit becomes less practical when the circuit becomes larger, we develop a method that makes use of circuit regularity. We prove that some small array of one-bit full adders, called the canonical configuration, has the same local optima as the n × n multiplier for large n, with the criterion of minimizing the delay time T. Hence, we can greatly reduce the computation load by optimizing this canonical configuration instead of optimizing the entire circuit. Experimental results confirm the effectiveness of this approach.

关键词： Adders Optimization methods Circuits MOS devices Very large scale integration programmable logic arrays Delay effects Digital signal processing chips Throughput Finite impulse response filter

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A NEW FAMILY OF MODULAR MICROCONTROLLERS WITH ON-CHIP SUPPORT FUNCTIONS

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1986年第3期21卷 400-403页

作者： BOCQUET, C MARQUOT, A GAUDRONNEAU, Y Eurotechnique Thomson Semiconductors Rousset France

This paper describes a new family of modular 4-bit microcontrollers that integrate on-chip support functions. Processed with 3-/spl mu/m NMOS technology, they offer very good trade-offs between speed and power consump... 详细信息

关键词： Microcontrollers Read only memory Central Processing Unit Registers Read-write memory programmable logic arrays Emulation MOS devices Energy consumption EPROM

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COMPUTER-AIDED MINIMIZATION PROCEDURE FOR BOOLEAN FUNCTIONS

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1986年第2期5卷 303-304页

作者： BISWAS, NN Department of Electrical Communication Engineering Indian Institute of Science Bangalore India

This paper describes the salient features of CAMP, a Computer Aided Minimization Procedure for single Boolean functions. The procedure is a divide and conquer algorithm, in which the essential prime implicants are first found, and then the best cover among the selective prime implicants are chosen. A significant feature of the algorithm is that the selection of the most suitable selective prime implicant to cover a minterm is based upon the information associated with the degree and direction of adjacency of the minterm itself. The generation of the complement of the function is not a requirement of the algorithm. The procedure has been implemented in a 250 line Fortran program. For shallow functions consisting mainly of essential prime implicants (EPI's) and a few selective prime implicants (SPI's), CAMP produces the exact or near minimal sum of product form. For dense functions consisting of a large number of interconnected cyclic SPI chains, a good minimal solution is obtained by minimizing the complementary function.

关键词： Boolean functions Minimization methods programmable logic arrays Very large scale integration Page description languages Integrated circuit interconnections logic design logic circuits Economic indicators Design automation

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A 19-NS 250-MW CMOS ERASABLE programmable logic DEVICE

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1986年第5期21卷 775-784页

作者： PATHAK, J KURKOWSKI, H PUGH, R SHRIVASTAVA, R JENNE, FB Cypress Semiconductors Inc. San Jose CA USA Apple Computer Inc. Cupertino CA USA

A 19-ns 250-mW erasable programmable logic device using 1.2-/spl mu/m n-well CMOS EPROM technology is described. CMOS EPROM technology and new circuit techniques give smaller die and lower power than SSI/MSI logic components without compromising speed. A novel cell current tracking, temperature-compensated sense amplifier is used to enhance performance and reduce power. The versatile macrocell makes the logic implementation simpler, and the EPROM technology gives improved programmability and reliability.

关键词： programmable logic devices CMOS technology EPROM Fuses Space technology Dielectric substrates logic devices Testing programmable logic arrays Threshold voltage

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PHYSIOlogicAL-ACTIVITY OF 1-AMINO-2-PHENYLETHYLPHOSPHONIC ACID, A SUBSTRATE-ANALOG OF PHENYLALANINE

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BIOLOGIA PLANTARUM 1986年第2期28卷 91-+页

作者： KNYPL, JS JANAS, KM 1.Plant Growth Substances Laboratory University of Lod? ul. Banacha 12/16 PL-90 237 Lod? Poland

1-Amino-2-phenylethylphosphonic acid (PheP) retards growth in Spirodela oligorrhiza causing morphological malformations, inhibits chlorophyll synthesis in progeny fronds, and markedly stimulates L-phenylalanine ammonia-lyase (PAL) activity in vivo and inhibits it in vitro;in prolonged experiments ribonuclease activity is stimulated. PheP severely inhibits anthrocyanin synthesis in seedlings of red cabbage, with moderate inhibition of PAL activity in vivo;chlorophyll synthesis and growth of the seedlings are little affected.

关键词： SHCBP1 gene Phenylalanine frond Phenylalanine Ammonia-Lyase Analog Analog PHYSIOlogicAL ACTIVITY programmable logic arrays synthesis growth Seedling LRIT1 gene RED CABBAGE Chlorophyll Ribonucleases

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