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检索条件"主题词=Programmable Logic Arrays"

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Design and implementation of an new Built-In Self-Test boundary scan architecture

Design and implementation of an new Built-In Self-Test bound...

引用

International Conference on Microelectronics, ICM

作者： M.H. El-Mahlawy E.A. El-Sehely A.S. Ragab S. Anas

The boundary scan (BS) technique offers a convenient alternative to physical probing. This paper presents new boundary scan architecture for Built-In Self-Test (BIST). The Boundary Scan Register (BSR) input cells have been configured to operate as a Test Pattern Generator (TPG) in the BIST mode. The BSR output cells have been configured to operate as a Multi-Input Shift Register (MISR) In the BIST mode. The Test Access Port Controller (TAPC) controls the BIST process. Instructions for BIST process are proposed. This configuration supports the BIST for both the Built-In logic Block Observer (BILBO) register and the register transfer level. This design Implemented on the Field programmable Gate Array (FPGA) Spartan X2C200 family.

关键词： Built-in self-test logic testing Registers System testing Circuit testing Pins Automatic testing Process control Field programmable gate arrays programmable logic arrays

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Hardware and Software Co-Processing Acceleration Architecture of Range Migration Algorithm for 3-D Millimeter-Wave Imaging

Hardware and Software Co-Processing Acceleration Architectur...

引用

IEEE International Conference on Computational Electromagnetics (ICCEM)

作者： Haoyi Yang Yang Meng Bocheng Chen Jun Li Guoping Chen Anyong Qing School of Optoelectronic Engineering Chongqing University of Posts and Telecommunications Chongqing China School of Electrical Engineering Southwest Jiaotong University Chengdu China

ISBN: (数字)9798350383317

ISBN: (纸本)9798350383324

The processing of millimeter-wave synthetic aperture radar (SAR) echo data plays a crucial role in target reconstruction, but it can be computationally time-consuming. To accelerate the reconstruction process, a solution is to leverage field-programmable gate arrays (FPGAs). However, due to the large size of the three-dimensional echo data (ranging from tens to hundreds of megabytes), it cannot be directly cached in the on-chip RAM of the FPGA. Instead, it can be stored in the DDR memory. To efficiently transfer multidimensional arrays from the processing system (PS) to the programmable logic (PL) using AXI-DMA, it is essential to rearrange the dimensions of the arrays. Unfortunately, implementing this operation directly on the FPGA can be challenging. To address this, this paper proposes an algorithm acceleration architecture that combines software and hardware co-processing. The computational part of the imaging algorithm is implemented in the PL section of the ZYNQ 7020 SoC, while the data permutation is performed by the PS.

关键词： Software algorithms Imaging Random access memory Computer architecture programmable logic arrays Millimeter wave radar Software

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A fast digital cluster finder and processor for high energy physics

A fast digital cluster finder and processor for high energy ...

引用

IEEE Symposium on Nuclear Science (NSS/MIC)

作者： B. Bylsma L.S. Durkin D. Larsen C. Lic T.Y. Ling S. Park C. Rush V. Sehgal R. Seidlein T.A. Romanowski

A hardwired processor dedicated to trigger processing in a typical modern high-energy physics experiment is described. Within this constraint, an attempt is made to maintain maximum flexibility. programmable logic and programmable gate arrays are used extensively, which allow improvements to be made without wiring changes. User-loadable lookup tables are used where possible to allow custom tweaking of the data processing. Examples from ZEUS and SDC are given to show how the basic architecture can be customized to these applications.< >

关键词： Hardware Clocks programmable logic arrays Fastbus Clustering algorithms Instruments Throughput Pipelines Proposals Geometry

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logic synthesis for programmable logic devices

Logic synthesis for programmable logic devices

引用

IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： T.-T. Hwang R.M. Owens M.J. Irwin Department of Computer Sciences Pennsylvania State University University Park PA USA

The use of communication complexity based logic synthesis when configuring programmable logic devices (PLDs) is discussed. Configuration of a PLD involves the two processes of logic synthesis and logic embedding. Since the allowable PLD logic primitives usually include a very large number of gates, the processes of logic synthesis and technology mapping cannot be completely decoupled as they normally are in traditional logic synthesis systems. The proposed communication-complexity-based logic synthesis tool has the advantage of not completely decoupling these two processes. It is more suited to PLD configuring than other multilevel logic synthesis methods.< >

关键词： programmable logic devices logic devices programmable logic arrays Switches Wires Very large scale integration Complexity theory Random access memory Computer science Helium

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Safety of VLSI designs using VHDL

Safety of VLSI designs using VHDL

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Annual Symposium on Reliability and Maintainability (RAMS)

作者： M. Pereira E. Soto Intelsis Sistemas Inteligentes S. A Santiago de Compostela Spain Universidad de Vigo Vigo Spain

This paper presents a methodology associated to a software tool to generate fail-safe VHDL synthesizable descriptions from Petri net or state diagrams. With this philosophy of automatically providing safety to VLSI systems design in VHDL, designers do not have to include the error detection system because it is going to be added automatically in the design. The method is explained as a group of sequential steps that transform a system into a fail-safe one. The tool uses a graphical environment to define the Petri net or state diagram. VHDL was chosen because is a standard widely supported by synthesis tools. The implementation of the circuit, which is valid either for programmable logic or ASICs, is done by other tools that support the VHDL standard. Following this methodology, three design parameters appear: size (consumption), speed, and safety level. Usually, every tool presents only optimization by speed and size. The proposed tool is fully implemented. VHDL code is synthesizable and experiments were made comparing unsafe and fail-safe systems in relation to their defining characteristics. Adding safety obviously supposes a heavy penalty in area occupied by the circuit. Future work should study the combination of other safety mechanisms, including the possibility of establishing a flexible level of safety.

关键词： Safety Very large scale integration Control systems Error correction codes Error correction Software tools Circuit synthesis programmable logic arrays programmable logic devices Hardware

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A mechanism to defend SYN flooding attack based on network measurement system

A mechanism to defend SYN flooding attack based on network m...

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International Conference on Information Technology: Research and Education (ITRE)

作者： Qiu Xiaofeng Hao Jihong Chen Ming Computer Department Institute of Command Automation People''s Liberation Army University of Science and Technology Nanjing China

SYN flooding attack is a common method employed in denial of service (DoS) and distributed denial of service (DDoS). It's hard to maintain the effective defense merely by passive defense measures such as monitoring and filtering. To avoid influencing the legitimate service requests and stop attacks at the source, the attack-detection and service-protection must be combined with the trace of the attack source. Having studied and concluded the features of such attacks, we propose a few key metrics to judge if an attack is undergoing. In this paper, the based platform, network measurement system (NMS) is outlined first. Then the detection method is discussed in detail, focusing on the features of service-protection, attack-elimination, and how to trace back the attack source. Finally, we present the experiments of the defending mechanism and analyze their results.

关键词： Floods TCPIP Computer networks Distributed computing Automation programmable logic arrays Computerized monitoring Modems Security Computer crime

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FPGAs and fault tolerance

FPGAs and fault tolerance

引用

International Conference on Microelectronics, ICM

作者： A. Doumar H. Ito Department of Information and Image Science Chiba University Japan

ISBN: (纸本)078037522X

In this paper we propose a modification of the standard structure of FPGA configuration memory cells in the torus structure. The proposed modification gives the FPGA the ability to shift the configuration data inside the chip as a torus structure. We show that FPGAs having this ability give better results in terms of test, diagnosis and defect/fault tolerance. Only faults occurring in configurable logic blocks are considered in this paper. Testing and diagnosing faults in the chips having the proposed modification are achieved by loading typically only one set of configuration data. The other configuration data required for test and diagnosis are obtained by shifting the first set inside the chip. This makes test and diagnosis faster. Our simulation results show that this way of testing is especially effective when the complexity of the configurable logic blocks or the size increases. On the other hand, the defect tolerance is transparent to the user and is achieved with a very high yield, while the fault tolerance is achieved on chip with the original user configuration data and without hardware intervention. Additionally, using 0.5 /spl mu/m technology, we have designed and manufactured a prototype of an FPGA similar to the Xilinx 4000 series structure having the ability to shift data.

关键词： Field programmable gate arrays Fault tolerance Manufacturing logic testing programmable logic arrays Very large scale integration Costs Circuits Automatic testing Laboratories

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A Q-Learning based sensing task selection scheme for cognitive radio networks

A Q-Learning based sensing task selection scheme for cogniti...

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International Conference on Wireless Communications and Signal Processing (WCSP)

作者： Mo Li Youyun Xu Junquan Hu Institute of Communications Engineering People''s Liberation Army University of Science and Technology Nanjing China

More than an adaptive system, the cognitive radio system should be a kind of intelligent system. In the paper, a Q-learning algorithm of the intelligent control theory is adopted to solve the sensing task selection problem among cognitive radio users in the distributed cognitive radio networks. In the proposed scheme, each cognitive radio user selects its sensing task through times of interaction with the environment and self-learning by means of its embedded Q-learning module. The scheme works without any CSI or estimation of primary traffic. According to the simulation results, the proposed scheme can improve the sensing efficiency and attain the convergence in a short time, so it may be regarded as a good attempt for the future intelligent cognitive radio systems.

关键词： Cognitive radio Chromium Control systems Intelligent systems Adaptive systems Telecommunication traffic Traffic control Data communication Radio control programmable logic arrays

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Information Encryption Security System Based on Chaos Algorithm

Information Encryption Security System Based on Chaos Algori...

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Cyber Security and Information Engineering (ICCSIE), International Conference on

作者： Xiya Liu Intelligent Manufacturing College Tianjin Sino-German University of Applied Sciences Tianjin China

ISBN: (纸本)9781665455756

Chaotic cryptography is structurally related to the concepts of confusion and diffusion in traditional cryptography theory. Chaotic cryptography is formed by the inevitable connection between chaos theory and pure cryptography. In order to solve the shortcomings of the existing research on information encryption security system, this paper discusses the realization technology of information security, the design principles of encryption system and three kinds of chaotic mapping systems, and discusses the selection of development tools and programmable devices. And the information encryption security system based on chaos algorithm is designed and discussed, and the randomness test of three groups of encrypted files is carried out by the proposed algorithm and the AES (Advanced Encryption Standard) algorithm. Experimental data show that the uniformity of P-value value of chaos algorithm is 0.714 on average. Therefore, it is verified that the information encryption security system using chaos algorithm has high security.

关键词： Chaos Performance evaluation programmable logic devices Information security Transforms programmable logic arrays logic gates

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A re-engineering approach to low power FPGA design using SPFD

A re-engineering approach to low power FPGA design using SPF...

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Design Automation Conference

作者： Jan-Min Hwang Feng-Yi Chiang TingTing Hwang Department of Computer Science Tsinghua University Hsinchu Taiwan

ISBN: (纸本)0897919645

In this paper, we present a method to re-synthesize look-up table (LUT) based Field programmable Gate arrays (FPGAs) for low power design after technology mapping, placement and routing are performed. We use Set of Pairs of Functions to be Distinguished (SPFD) to express functional permissibility of each signal. Using different propagations of SPFD: to fan-in signals, we change the functionality of a PLB (programmable logic Block) which drives large loading into one with low transition density. Experimental results show that our method can reduce on average 12% power consumption compared to the original circuits without affecting placement and routing.

关键词： Field programmable gate arrays Routing Circuits Table lookup Permission Plasma welding Energy consumption Computer science programmable logic arrays programmable logic devices

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