The 96 input channels are multiplexed to six (12 bits) converters in such a way that adjacent channels are driven to different chips. The maximum conversion time is 65 μs. Common analog threshold for zero suppression...
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The 96 input channels are multiplexed to six (12 bits) converters in such a way that adjacent channels are driven to different chips. The maximum conversion time is 65 μs. Common analog threshold for zero suppression is available with possible choice of neighbours to be converted. The threshold action can be disabled by external input command (or CSR # 0 status). S.R. and broadcasts are implemented.
A computer program is presented that translates logic equations into promburner files (or the reverse) for programmablelogic devices of various kinds, namely PROMs FPLAs, FPLSs and PALs. The program achieves flexibil...
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A computer program is presented that translates logic equations into promburner files (or the reverse) for programmablelogic devices of various kinds, namely PROMs FPLAs, FPLSs and PALs. The program achieves flexibility through the use of a database containing detailed information about the devices to be programmed. New devices can thus be accommodated through simple extensions of the database. When writing logic equations, the user can define logic combinations of signals as new logic variables for use in subsequent equations. This procedure yields compact and transparent expressions for logic operations, thus reducing the chances for error. A logic simulation program is also provided so that an independent check of the design can be performed at the software level.
A 256-word/spl times/32-bit associated memory, referred to as the Content Addressable and Reentrant Memory (CARM), with a 100-ns cycle time is described. The high bit density of the device is realized by a small-size ...
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A 256-word/spl times/32-bit associated memory, referred to as the Content Addressable and Reentrant Memory (CARM), with a 100-ns cycle time is described. The high bit density of the device is realized by a small-size associative memory cell (30/spl times/36 /spl mu/m/SUP 2/) with 2-/spl mu/m CMOS technology, while a double-layer metallization technique, new circuits for the control-signal propagation, and a hierarchical structure for the address encoder of the chip allow fast access. This device has reentrant mode operation, where the on-chip garbage collection or data storage is accomplished conditionally. One of the practical applications of this device, a high-speed matching unit for dataflow computers, is also discussed.
Computer-Aided synthesis of sequential functions of VLSI systems, such as microprocessor control units, must include design optimization procedures to yield area-effective circuits. We model sequential functions as de...
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Computer-Aided synthesis of sequential functions of VLSI systems, such as microprocessor control units, must include design optimization procedures to yield area-effective circuits. We model sequential functions as deterministic synchronous Finite State Machines (FSM's), and we consider a regular and structured implementation by means of programmable logic arrays (PLA's) and feedback registers. State assignment, i.e., binary encoding of the internal states of the finite state machine, affects substantially the silicon area taken by such an implementation. Several state assignment techniques have been proposed in the past. However, to the best of our knowledge, no Computer-Aided Design tool is in use today for an efficient encoding of control logic. We propose an algorithm for optimal state assignment. Optimal state assignment is based on an innovative strategy: logic minimization of the combinational component of the finite state machine is applied before state encoding. logic minimization is performed on a symbolic (code independent) description of the finite state machine. The minimal symbolic representation defines the constraints of a new encoding problem, whose solutions are the state assignments that allow the implementation of the PLA with at most as many product-terms as the cardinality of the minimal symbolic representation. In this class, an optimal encoding is one of minimal length satisfying these constraints. A heuristic algorithm constructs a solution to the constrained encoding problem. The algorithm has been coded in a computer program, KISS, and tested on several examples of finite state machines. Experimental results have shown that the method is an effective tool for designing finite state machines.
A semi-custom (gate array) integrated circuit has been designed for use in the SLAC Linear Collider timing and control system. The design process and SLAC's experiences during the phases of the design cycle are de...
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A semi-custom (gate array) integrated circuit has been designed for use in the SLAC Linear Collider timing and control system. The design process and SLAC's experiences during the phases of the design cycle are described. Issues concerning the partitioning of the design into semi-custom and standard components are discussed. Functional descriptions of the semi-custom integrated circuit and the timing module in which it is used are given.
A 10-kH and 100K ECL compatible field programmable array logic IC with 3.6-ns propagation delay and 1.0-W power dissipation has been developed. The device is organized as 12 inputs, 64 product terms, four outputs, and...
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A 10-kH and 100K ECL compatible field programmable array logic IC with 3.6-ns propagation delay and 1.0-W power dissipation has been developed. The device is organized as 12 inputs, 64 product terms, four outputs, and four bidirectional I/Os. The device also features the ability to complement the output by programming the polarity. To facilitate field programming and testing, an on-chip PLA causes the device to emulate a TTL compatible 2048/spl times/1-bit PROM, and the PLA is also used to control the device in test modes of operations to enhance the testability. The excellent speed-power performance has been realized by use of an oxide-isolated dual-layer metal process and an optimized circuit design.
Solving the minimal covering problem by an implicit enumeration method is discussed. The implicit enumeration method in this paper is a modification of the Quine-McCluskey method tailored to computer processing and al...
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Solving the minimal covering problem by an implicit enumeration method is discussed. The implicit enumeration method in this paper is a modification of the Quine-McCluskey method tailored to computer processing and also its extension, utilizing some new properties of the minimal covering problem for speedup. A heuristic algorithm is also presented to solve large-scale problems. Its application to the minimization of programmable logic arrays (i.e., PLAs) is shown as an example. Computational experiences are presented to confirm the improvements by the implicit enumeration method discussed.
A novel single transistor electrically alterable memory cell is presented. The cell is based on floating gate technology using a double diffused (DMOS) transistor. Writing into the cell is achieved through hot electro...
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A novel single transistor electrically alterable memory cell is presented. The cell is based on floating gate technology using a double diffused (DMOS) transistor. Writing into the cell is achieved through hot electron injection while erasing is performed via Fowler-Nordheim tunneling through a thin oxide (100-Å) region. The memory cell requires only one transistor because the write and erase voltages range between 15-20 and 25-30 V, respectively. The writeability of the cell is enhanced by the thin oxide region and dependent on the proximity of this region to the channel of the DMOS transistor.
This paper presents new algorithms for routing two rows of interchangeable terminals across a 2-layer channel. The number of horizontal tracks required for routing is significantly reduced by simply interchanging term...
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This paper presents new algorithms for routing two rows of interchangeable terminals across a 2-layer channel. The number of horizontal tracks required for routing is significantly reduced by simply interchanging terminals in each cell. Savings up to one-third of horizontal tracks or more are achieved by interchanging terminals. The Deutsch Difficult Example is used as a test routing problem. The number of horizontal segments per net is limited to one, no "doglegs." The program is coded in Pascal and implemented on a VAX-11/780 computer.
In any bus system, it is desirable to implement the basic bus protocol with a standard interface. The paper describes such an interface which has been developed for FASTBUS Slave modules. The interface supports all FA...
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In any bus system, it is desirable to implement the basic bus protocol with a standard interface. The paper describes such an interface which has been developed for FASTBUS Slave modules. The interface supports all FASTBUS Address and Data Cycles. Major parts of the interface have been implemented in programmable array logic (PALs*) which reduces the space occupied by the interface to less than 10% of the board area.
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