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检索条件"主题词=Programmable Logic Arrays"
4439 条 记 录,以下是4171-4180 订阅
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ADC FASTBUS 12 BITS-96 CHANNELS (ID-F6829)
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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 1985年 第4期32卷 1339-1340页
作者: BELLEMAIN, A AUGE, E HEUSSE, P Laboratoire de l'Accélérateur Linéaire Université de Paris-Sud Orsay France
The 96 input channels are multiplexed to six (12 bits) converters in such a way that adjacent channels are driven to different chips. The maximum conversion time is 65 μs. Common analog threshold for zero suppression... 详细信息
来源: 评论
UNIVERSAL FILE PROCESSING PROGRAM FOR FIELD programmable INTEGRATED-CIRCUITS
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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 1985年 第1期32卷 332-335页
作者: FREYTAG, DR NELSON, DJ Stanford Linear Accelerator Center University of Stanford Stanford CA USA
A computer program is presented that translates logic equations into promburner files (or the reverse) for programmable logic devices of various kinds, namely PROMs FPLAs, FPLSs and PALs. The program achieves flexibil... 详细信息
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AN 8-KBIT CONTENT-ADDRESSABLE AND REENTRANT MEMORY
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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1985年 第5期20卷 951-957页
作者: KADOTA, H MIYAKE, J NISHIMICHI, Y KUDOH, H KAGAWA, K Semiconductor Research Center Matsushita Elecrric Indusrrial Company Limited Moriguchi Osaka Japan
A 256-word/spl times/32-bit associated memory, referred to as the Content Addressable and Reentrant Memory (CARM), with a 100-ns cycle time is described. The high bit density of the device is realized by a small-size ... 详细信息
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OPTIMAL STATE ASSIGNMENT FOR FINITE STATE MACHINES
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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1985年 第3期4卷 269-285页
作者: DEMICHELI, G BRAYTON, RK SANGIOVANNIVINCENTELLI, A UNIV CALIF BERKELEY DEPT ELECT ENGN & COMP SCI BERKELEY CA 94720 USA
Computer-Aided synthesis of sequential functions of VLSI systems, such as microprocessor control units, must include design optimization procedures to yield area-effective circuits. We model sequential functions as de... 详细信息
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THE DESIGN OF A SEMI-CUSTOM INTEGRATED-CIRCUIT FOR THE SLAC SLC TIMING CONTROL-SYSTEM
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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 1985年 第1期32卷 87-88页
作者: LINSTADT, E Stanford Linear Accelerator Center Stanford CA USA
A semi-custom (gate array) integrated circuit has been designed for use in the SLAC Linear Collider timing and control system. The design process and SLAC's experiences during the phases of the design cycle are de... 详细信息
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A 3.6-NS ECL FIELD programmable ARRAY logic DEVICE
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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1985年 第5期20卷 1036-1042页
作者: MILLHOLLAN, MS SUNG, C National Semiconductor Santa Clara CA USA
A 10-kH and 100K ECL compatible field programmable array logic IC with 3.6-ns propagation delay and 1.0-W power dissipation has been developed. The device is organized as 12 inputs, 64 product terms, four outputs, and... 详细信息
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MINIMAL COVERING PROBLEM AND PLA MINIMIZATION
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INTERNATIONAL JOURNAL OF COMPUTER & INFORMATION SCIENCES 1985年 第6期14卷 337-364页
作者: YOUNG, MH MUROGA, S UNIV ILLINOIS DEPT COMP SCIURBANAIL 61801
Solving the minimal covering problem by an implicit enumeration method is discussed. The implicit enumeration method in this paper is a modification of the Quine-McCluskey method tailored to computer processing and al... 详细信息
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A SINGLE TRANSISTOR ELECTRICALLY ALTERABLE CELL
IEEE ELECTRON DEVICE LETTERS
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IEEE ELECTRON DEVICE LETTERS 1985年 第10期6卷 519-521页
作者: CACHARELIS, P FONG, E TORGERSON, E CONVERSE, MJ DENHAM, P ADV MICRO DEVICES INC SUNNYVALECA 94086 GEN INSTRUMENTS PALO ALTOCA 94304 SEMI PROCESSES INC SAN JOSECA 95132
A novel single transistor electrically alterable memory cell is presented. The cell is based on floating gate technology using a double diffused (DMOS) transistor. Writing into the cell is achieved through hot electro... 详细信息
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EFFICIENT ALGORITHMS FOR ROUTING INTERCHANGEABLE TERMINALS
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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1985年 第3期4卷 204-207页
作者: KOBAYASHI, H DROZD, CE Department of Electrical and Computer Engineering University of South Carolina Columbia SC USA
This paper presents new algorithms for routing two rows of interchangeable terminals across a 2-layer channel. The number of horizontal tracks required for routing is significantly reduced by simply interchanging term... 详细信息
来源: 评论
A SIMPLE FASTBUS SLAVE INTERFACE USING PALS
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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 1985年 第1期32卷 325-327页
作者: DOWNING, RW PREGERNIG, L CERN CH-1211 GENEVA 23SWITZERLAND
In any bus system, it is desirable to implement the basic bus protocol with a standard interface. The paper describes such an interface which has been developed for FASTBUS Slave modules. The interface supports all FA... 详细信息
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