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检索条件"主题词=Programmable Logic Arrays"

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A 145 MHz user-programmable gate array

A 145 MHz user-programmable gate array

引用

International Workshop on Rapid System Prototyping (RSP)

作者： E. do Valle Simoes D.A.C. Barone Federal University of Rio Grande do Sul Porto Alegre Brazil

This work aims to present the most relevant results derived from the development of a novel FPGA matrix. Nevertheless its capacity, its highlights are low cost and its ability to deal with high frequencies. This prototype matrix, named FLECHA, presents some structural novelties, as a different approach to perform the interconnections between logic cells and I/O pads and an internal controller. One of the major contributions of this work deals with the strategy of placing the logic cells in rows, allowing a drastic reduction of the number of switches without reducing interconnection capacity between logic cells and I/O pads. Following this principle, a new matrix presenting 600 equivalent gates was constructed including 40 logic cells and 40 programmable I/O pads. The FLECHA matrix is intended to implement simple logic functions as for fast "glue logic" between processors and memories, reaching an operational frequency of l45 MHz.

关键词： logic arrays Field programmable gate arrays Prototypes Switches programmable logic arrays Costs Frequency logic functions logic devices Signal processing

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Managing Health Information Flows with a Reconfigurable Component-Based Middleware

Managing Health Information Flows with a Reconfigurable Comp...

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International Conference on Mobile Data Management

作者： Jatinder Singh Jean Bacon Computer Laboratory University of Cambridge UK

Healthcare is becoming increasingly pervasive. Improvements in sensor and mobile communication technologies allow for the constant monitoring of patients and their environment. Infrastructure supporting care services must enable such data to flow to the relevant parties as appropriate to the circumstances. This paper describes our initial work on a policy driven, component-based middleware, illustrating how it manages information flows (through reconfiguration) to account for the dynamic nature of healthcare provisioning.

关键词： Middleware programmable logic arrays Engines Medical services Databases Context Monitoring

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Mapping algorithms onto the TUT cellular array processor

Mapping algorithms onto the TUT cellular array processor

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International Conference on Application Specific Array Processors

作者： J. Viitanen T. Korpiharju J. Takala H. Kliminkinen Tampere University of Technology Tampere Finland Tampere Univ. of Technol. Finland

The Tampere University of Technology Cellular Array (TUTCA) processor array is based on a dynamically configurable logic cell array. It is intended for efficient implementation of the direct mapping dataflow principle with a self-timed, distributed control structure. The architecture of the processor, principles of mapping algorithms on it, and the compiler of the dataflow language are described. The language used for programming is a slightly modified version of DFL. The main features of DFL, the parser, the array processing, the graph structure generated by DFL, and the performance and exploitation of parallelism are considered.< >

关键词： logic arrays Processor scheduling programmable logic arrays Hardware logic devices logic circuits logic programming Distributed control Data communication Flow graphs

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Developing Flexible 3D Printed Antenna Using Conductive ABS Materials

Developing Flexible 3D Printed Antenna Using Conductive ABS ...

引用

IEEE International Symposium on Antennas and Propagation

作者： Milad Mirzaee Sima Noghanian Lindsey Wiest Isaac Chang Department of Electrical Engineering University of North Dakota Grand Forks ND USA Department of Technology University of North Dakota Grand Forks ND USA

ISBN: (纸本)9781479978168

This paper presents the feasibility of conductive acrylonitrile butadiene styrene (ABS) materials in the fabrication of flexible three-dimensional (3D) antennas using additive manufacturing method. To demonstrate this application a bowtie antenna with coplanar waveguide (CPW) feed structure has been designed and measured. The prototype of the antenna has been fabricated using Makerbot dual 3D printer and flexible polylactic acid (PLA) and ABS filaments for dielectric and conductive parts of the antenna, respectively. To our knowledge, this is the first reported antenna fabricated with conductive ABS material. The dielectric properties of the PLA and ABS filaments have been measured using Agilent performance probe. The fabricated antenna possesses compact size, light-weight and mechanically flexible structure. In addition it achieves wide bandwidth of 24.18 % at the center frequency of 7.81 GHz.

关键词： ABS resins DDX41 gene Antilock Braking Systems ANTENNA antennae center frequency conductivity bow-tie antennas 3D Printer programmable logic arrays Microstrip antennas fabrication FLEXIBLE coplanar waveguides

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PLA-based runtime dynamism in support of privacy-enhanced Web personalization

PLA-based runtime dynamism in support of privacy-enhanced We...

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International Software Product Line Conference (SPLC)

作者： Yang Wang A. Kobsa A. van der Hoek J. White Department of Informatics Donald Bren School of Information and Computer Sciences University of California Irvine CA USA

Software product line architectures (PLAs) have been widely recognized as a successful approach in industrial software development for improving productivity, software quality and time-to-market. In this paper, we focus on the usage of a PLA for a quite different purpose, namely, handling privacy constraints in Web personalization. To provide personalized services such as customized recommendations, a personalized Website collects users' personal data, which raises various privacy concerns. We aim at reconciling the benefits of web personalization with privacy constraints that come from users themselves as well as from privacy legislations and regulations that apply to a given user. We propose a dynamic, privacy-enabling personalization infrastructure and conceive it as a PLA. This infrastructure allows for dynamically selecting and instantiating personalization architectures that provide personalized services to each individual user and comply with the prevailing privacy constraints

关键词： Runtime programmable logic arrays Software quality Computer architecture Computer industry Programming Productivity Time to market Data privacy Legislation

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Testing a Transistor-Level programmable Fabric: Challenges and Solutions

Testing a Transistor-Level Programmable Fabric: Challenges a...

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VLSI Test Symposium

作者： Apurva Jain Thomas Broadfoot Carl Sechen Yiorgos Makris Electrical and Computer Engineering Dept. The University of Texas at Dallas Richardson TX USA

ISBN: (数字)9798350363784

ISBN: (纸本)9798350363791

Test vector generation for a TRAnsistor-level programmable (TRAP) fabric faces a number of feasibility and efficiency challenges. The former are caused by (i) the use of bi-directional pass transistors, which are beyond the capabilities of commercial Automatic Test Pattern Generation (ATPG) tools, and (ii) the design specifics of TRAP, which result in certain stuck-at faults not being logically testable and calling for a quiescent current-based test solution instead. The latter are caused by the fact that ATPG tools are oblivious to (i) the difference between programming bits and regular inputs, which results in lengthy test application times, and (ii) the role that different modules in the architecture of TRAP play in establishing logic circuits, which results in lengthy unguided exploration of a very large functional space to establish appropriate vector justification and response propagation paths. To address these challenges, we explore an array of solutions including (i) employing TRAP instances where bi-directional transistors are replaced by uni-directional ones, (ii) generating custom IDDQ tests, (iii) expressing test application time as the optimization objective of an Integer Linear Program (ILP) formulation, and (iv) leveraging design knowledge, resulting in perfect stuck-at fault coverage of TRAP and an order-of-magnitude savings in test application time.

关键词： Bidirectional control programmable logic arrays Automatic test pattern generation Very large scale integration Programming Vectors Fabrics

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A Congestion Driven Placement Algorithm for FPGA Synthesis

A Congestion Driven Placement Algorithm for FPGA Synthesis

引用

International Conference on Field programmable logic and Applications

作者： Yue Zhuo Hao Li Saraju P. Mohanty Department of Computer Science and Engineering University of North Texas Denton TX USA

We introduce a new congestion driven placement algorithm for FPGAs in which the overlapping effect of bounding boxes is taken into consideration. Experimental results show that compared with the linear congestion method (Betz et al., 1999) used in the state-of-the-art FPGA place and route package VPR (Betz and Rose, 1997), our algorithm achieves channel width reduction on 70% of the 20 largest MCNC benchmark circuits (10.1% on average) while keeping the channel width of the remaining 30% benchmarks unchanged. A distinct feature of our algorithm is that the critical path delay is not elongated on average, and in most cases reduced

关键词： Field programmable gate arrays Routing Delay Application specific integrated circuits Clustering algorithms Simulated annealing Computer science Packaging programmable logic arrays Wires

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Comparative Study on Different Schemes for Treatment with Multi-Islands and Complex Coastlines in Wave Numerical Computation

Comparative Study on Different Schemes for Treatment with Mu...

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International Conference on Information Science and Engineering (ICISE)

作者： Ke-feng Mao Xi Chen Yan Li Zhong-le Xiao Inst. of Meteorol. PLA Univ. of Sci. & Tech. Nanjing China No.96631 army of PLA Beijing China

In order to describe complex multi-island terrain and coastlines adequately in ocean wave numerical model, basing on the optimization of computing grid by using depth and high resolution coastlines, the method of introducing sub-grid effect into WAVEWATCH-III model has been established. Comparing the results of computation with this scheme and with the scheme for improving grid resolution to distinguish out islands, it shows that: The effect of multi-islands and complex terrain on wave spreading is adequately described by sub-grid effect of islands and the results are much better; The computational precision of significant wave height obtained by introducing the scheme for sub-grid effect of islands into computation with low resolution grid is equivalent with the precision of results obtained by computation with high resolution grid, but the efficiency of former scheme is greatly improved.

关键词： Grid computing Spatial resolution Military computing Distributed computing Ocean waves Equations programmable logic arrays Information science Meteorology Numerical models

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A "soft++" eFPGA physical design approach with case studies in 180nm and 90nm

A "soft++" eFPGA physical design approach with case studies ...

引用

IEEE Computer Society Annual Symposium on VLSI

作者： V. Aken'Ova R. Saleh Department of Electrical and Computer Engineering University of British Columbia Vancouver BC Canada

Our recent work in embedded FPGAs has been focused on a soft IP approach where programmable fabrics are described at the RTL level and implemented using the ASIC digital flow and generic standard cells. Early results showed significant penalties in area, delay, and power overhead. However, using tactical standard cells and a structured physical design approach within such a flow, we were able to obtain large savings in area and delay. We defined this new approach as soft++ eFPGA. This paper provides details of the physical design flow, with particular emphasis on floor-planning, interconnect-planning, and clock tree synthesis. The advantages of our approach in handling larger circuits are demonstrated on a set of realistic benchmark circuits implemented in 180nm and 90nm CMOS process technology

关键词： Computer aided software engineering Field programmable gate arrays Fabrics Application specific integrated circuits Delay Integrated circuit interconnections programmable logic arrays Costs logic design programmable logic devices

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A new multilevel hierarchical MFPGA and its suitable configuration tools

A new multilevel hierarchical MFPGA and its suitable configu...

引用

IEEE Computer Society Annual Symposium on VLSI

作者： Z. Marrakchi H. Mrabet H. Mehrez Department ASIM-LIP6 Université Paris 6-Pierre et Marie Curie Paris France

In this paper we evaluate a new multilevel hierarchical MFPGA. The specific architecture includes two unidirectional programmable networks. A downward network based on the butterfly-fat-tree topology, and a special rising network. New tools are developed to place and route several benchmark circuits on this architecture. Comparison with the traditional symmetric, Manhattan mesh architecture shows that MFPGA can implement circuits with fewer switches and a smaller area.

关键词： Switches Field programmable gate arrays Routing Joining processes Network topology programmable logic arrays Integrated circuit interconnections Circuit topology Switching circuits logic arrays

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