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检索条件"主题词=Programmable Logic Arrays"

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Comparative Study on Different Schemes for Treatment with Multi-Islands and Complex Coastlines in Wave Numerical Computation

Comparative Study on Different Schemes for Treatment with Mu...

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International Conference on Information Science and Engineering (ICISE)

作者： Ke-feng Mao Xi Chen Yan Li Zhong-le Xiao Inst. of Meteorol. PLA Univ. of Sci. & Tech. Nanjing China No.96631 army of PLA Beijing China

In order to describe complex multi-island terrain and coastlines adequately in ocean wave numerical model, basing on the optimization of computing grid by using depth and high resolution coastlines, the method of introducing sub-grid effect into WAVEWATCH-III model has been established. Comparing the results of computation with this scheme and with the scheme for improving grid resolution to distinguish out islands, it shows that: The effect of multi-islands and complex terrain on wave spreading is adequately described by sub-grid effect of islands and the results are much better; The computational precision of significant wave height obtained by introducing the scheme for sub-grid effect of islands into computation with low resolution grid is equivalent with the precision of results obtained by computation with high resolution grid, but the efficiency of former scheme is greatly improved.

关键词： Grid computing Spatial resolution Military computing Distributed computing Ocean waves Equations programmable logic arrays Information science Meteorology Numerical models

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Testing a Transistor-Level programmable Fabric: Challenges and Solutions

Testing a Transistor-Level Programmable Fabric: Challenges a...

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VLSI Test Symposium

作者： Apurva Jain Thomas Broadfoot Carl Sechen Yiorgos Makris Electrical and Computer Engineering Dept. The University of Texas at Dallas Richardson TX USA

ISBN: (数字)9798350363784

ISBN: (纸本)9798350363791

Test vector generation for a TRAnsistor-level programmable (TRAP) fabric faces a number of feasibility and efficiency challenges. The former are caused by (i) the use of bi-directional pass transistors, which are beyond the capabilities of commercial Automatic Test Pattern Generation (ATPG) tools, and (ii) the design specifics of TRAP, which result in certain stuck-at faults not being logically testable and calling for a quiescent current-based test solution instead. The latter are caused by the fact that ATPG tools are oblivious to (i) the difference between programming bits and regular inputs, which results in lengthy test application times, and (ii) the role that different modules in the architecture of TRAP play in establishing logic circuits, which results in lengthy unguided exploration of a very large functional space to establish appropriate vector justification and response propagation paths. To address these challenges, we explore an array of solutions including (i) employing TRAP instances where bi-directional transistors are replaced by uni-directional ones, (ii) generating custom IDDQ tests, (iii) expressing test application time as the optimization objective of an Integer Linear Program (ILP) formulation, and (iv) leveraging design knowledge, resulting in perfect stuck-at fault coverage of TRAP and an order-of-magnitude savings in test application time.

关键词： Bidirectional control programmable logic arrays Automatic test pattern generation Very large scale integration Programming Vectors Fabrics

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A Congestion Driven Placement Algorithm for FPGA Synthesis

A Congestion Driven Placement Algorithm for FPGA Synthesis

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International Conference on Field programmable logic and Applications

作者： Yue Zhuo Hao Li Saraju P. Mohanty Department of Computer Science and Engineering University of North Texas Denton TX USA

We introduce a new congestion driven placement algorithm for FPGAs in which the overlapping effect of bounding boxes is taken into consideration. Experimental results show that compared with the linear congestion method (Betz et al., 1999) used in the state-of-the-art FPGA place and route package VPR (Betz and Rose, 1997), our algorithm achieves channel width reduction on 70% of the 20 largest MCNC benchmark circuits (10.1% on average) while keeping the channel width of the remaining 30% benchmarks unchanged. A distinct feature of our algorithm is that the critical path delay is not elongated on average, and in most cases reduced

关键词： Field programmable gate arrays Routing Delay Application specific integrated circuits Clustering algorithms Simulated annealing Computer science Packaging programmable logic arrays Wires

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A layout-aware synthesis methodology for RF circuits 01

A layout-aware synthesis methodology for RF circuits

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IEEE International Conference on Computer-Aided Design

作者： P. Vancorenland G. Van der Plas M. Steyaert G. Gielen W. Sansen Department of Electrical Engineering ESAT MICAS Katholieke Universiteit Leuven Leuven Belgium

ISBN: (纸本)9780780372498

In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling and integrated layout generation to synthesize RF Circuits efficiently, taking into account all layout parasitics during the circuit optimization. The proposed approach has successfully been applied to the design of a high-performance downconverter mixer circuit, proving the effectiveness of the implemented design methodology.

关键词： Circuit synthesis Radio frequency Design optimization Circuit simulation Central Processing Unit Integrated circuit synthesis Circuit noise programmable logic arrays Cost function Power generation

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PLA-based runtime dynamism in support of privacy-enhanced Web personalization

PLA-based runtime dynamism in support of privacy-enhanced We...

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International Software Product Line Conference (SPLC)

作者： Yang Wang A. Kobsa A. van der Hoek J. White Department of Informatics Donald Bren School of Information and Computer Sciences University of California Irvine CA USA

Software product line architectures (PLAs) have been widely recognized as a successful approach in industrial software development for improving productivity, software quality and time-to-market. In this paper, we focus on the usage of a PLA for a quite different purpose, namely, handling privacy constraints in Web personalization. To provide personalized services such as customized recommendations, a personalized Website collects users' personal data, which raises various privacy concerns. We aim at reconciling the benefits of web personalization with privacy constraints that come from users themselves as well as from privacy legislations and regulations that apply to a given user. We propose a dynamic, privacy-enabling personalization infrastructure and conceive it as a PLA. This infrastructure allows for dynamically selecting and instantiating personalization architectures that provide personalized services to each individual user and comply with the prevailing privacy constraints

关键词： Runtime programmable logic arrays Software quality Computer architecture Computer industry Programming Productivity Time to market Data privacy Legislation

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Methodology for Characterization of NOR-NOR programmable logic Array

Methodology for Characterization of NOR-NOR Programmable Log...

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Asia International Conference on Modeling & Simulation

作者： Venkata Rajesh Mekala Venkata Rakesh Mekala Department of Electrical and Computer Engineering College Station Department of Electronics and Instrumentation Engineering JNTU-Hyderabad

programmable logic arrays are popular implementations for "multi-input" 2-level "multi- output" functions. PLAs are advantageous for designers especially in GHz technology with deep sub-micron sizing. The regular structures of PLAs are attractive to VLSI designers because they require a small number of separate cell designs. PLAs allow "ease of testing". The biggest advantage is that the entire design flow in the PLA generation can be automated. The main focus of the paper is to establish a quick design verification methodology for *** choose dynamic PLAs which have an advantage of higher frequency of operation, lesser power consumption and easier predictability of area. The methodology involves generation of spice decks dynamically using Perl code and simulating the PLA's pre-layout net-list in H-Spice. In the post-layout stage layouts are dynamically generated using SKILL programming in Virtuoso and simulating post-layout net-list in H-Spice. Various characterization experiments are done on PLA using this methodology.

关键词： programmable logic arrays

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Improving response time of programmable logic controllers by use of a Boolean coprocessor

Improving response time of programmable logic controllers by...

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CompEuro

作者： J. Donandt AEG Research Institute Berlin Berlin Germany

ISBN: (纸本)0818619406

programmable-logic controllers (PLCs) are widely used to control technical processes in the industrial environment. In the requirements for next-generation PLCs, their fast response to events from the controlled processes plays a central role. The author shows that the response time of a low-cost PLC can be shortened by at least a factor of ten by using a special Boolean coprocessor in conjunction with the PLC (micro-) processor. The speedup is achieved by two means: (1) an architecture of the Boolean coprocessor designed for very fast execution of instructions on bit data, and (2) parallel execution of bit- and word-instruction streams with an efficient synchronization mechanism between them. The Boolean coprocessor's design is completed at the register transfer level. Simulation at the register transfer level and a gate-level simulation of the critical data path indicate an instruction-cycle time of less than 0.3 mu s. The VLSI realization of the design requires a gate array of 4000 gates with a 2-kb fast on-chip RAM.< >

关键词： Delay Boolean functions programmable logic arrays programmable logic devices programmable control Coprocessors Process control Microprocessors Industrial control Centralized control

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CSDL & GLIDER: Tools for implementing cellular structures into FPGAs

CSDL & GLIDER: Tools for implementing cellular structures in...

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IEEE International Caracas Conference on Devices, Circuits and Systems

作者： Nestor Ferrando Jodar Joaquin Cerda Boluda Rafael Gadea Girones Vicente Herrero Bosch Electronic Engineering Department Universidad Politecnica de Valencia Valencia Spain

Cellular Automata (CA) consist of a lattice of discrete identical sites called cells, each one taking a value from a finite set. The values of the cells evolve in discrete steps according to deterministic rules that specify the value of the cell in terms of the values of the neighboring sites. Due to its massive parallelism, CA are not appropriated to be implemented on classical, sequential resources such as microprocessors, but adapt better to digital electronic structures such as FPGAs. In this paper, Cellular Structure Description Language (CSDL) and Glider are presented. CSDL is a language specifically oriented to define a wide range of cellular nets. CSDL allows defining a cell and describing the interconnection between cells by simply selecting a topological distribution and mapping inputs to outputs in a regular way. After compilation, a CSDL file can be used in several development systems, both for software, simulation purposes or for hardware implementation.

关键词： Field programmable gate arrays Hardware programmable logic arrays Java Cellular networks Circuits and systems Lattices Microprocessors Integrated circuit interconnections LAN interconnection

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Synthesis of the Growth Hormone Secretion Mechanism Using Nonlinear Analysis and CAD Tools

Synthesis of the Growth Hormone Secretion Mechanism Using No...

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Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)

作者： J.R. Shell Department of Electrical Engineering Southem Illinois University Carbondale IL USA

The goal of this paper is to present a hardware realization of the feed-forward and feedback hypothalamic-pituitary growth hormone (GH) secretion mechanism based on a bio-mathematical nonlinear delay differential equation model developed by Farhy et al. (2003) and Veldhuis et al. (2001). Behavioral modeling is implemented through Verilog hardware descriptive language (HDL) to simulate the antagonistic and stimulatory interaction of growth hormone, growth hormone releasing hormone (GHRH) and somatotropin release inhibiting factor (SRIF). The model is synthesized using computer aided design (CAD) tools and is promulgated through a combinational complex programmable logic device (CPLD)/field programmable grid array (FPGA) Xilinx XSA-50 microchip. The microchip sequentially displays the decimal equivalents of the time changing hormonal concentration levels of the biomathematical model

关键词： Biochemistry Fluids and secretions Hardware design languages programmable logic arrays Feedforward systems Feedback Delay Differential equations Computational modeling Grid computing

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Splicer: a heuristic approach to connectivity binding

Splicer: a heuristic approach to connectivity binding

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Design Automation Conference

作者： B.M. Pangrle Department of Electrical and Computer Engineering University of California Santa Barbara CA USA

A tool is described for constructing the connectivity between components given a state graph into which the components are to be mapped. Examples taken from previous papers in the field are used to demonstrate this connectivity binder. The results point to heuristics that are used to generate solutions to the problem. Questions addressed include how much of the state graph must be considered at one time to give reasonable results and how the search space can be prune to achieve good solutions quicker. The code for this project is written in C and runs under 4.2 BSD Unix.< >

关键词： High level synthesis Synthesizers Flow graphs Hardware Buildings Silicon compiler Read-write memory Read only memory programmable logic arrays Filling

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