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ON THE SIZE OF PLAS REQUIRED TO REALIZE BINARY AND MULTIPLE-VALUED FUNCTIONS

IEEE TRANSACTIONS ON COMPUTERS 1989年第1期38卷 82-98页

作者： BENDER, EA BUTLER, JT USN POSTGRAD SCHDEPT ELECT & COMP ENGNMONTEREYCA 93943

Upper and lower bounds are shown for the average number of product terms required in the minimal realization, as a function of the number of nonzero output values. The variance, in addition to the bounds, allows conclusions to be drawn about how PLA size determines the set of realizable functions. Although the bounds are most accurate when there are few nonzero values, they are adequate for analyzing commercially available PLAs. The analysis shows that, for all but one commercially available PLA, the number of nonzero values is a statistically meaningful criterion for determining whether or not a given function is likely to be realized.

关键词： programmable logic arrays Nonzero Lower bound multi-value Binary Bound minimal realization

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PLA FOLDING BY SIMULATED ANNEALING

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1987年第2期22卷 208-215页

作者： WONG, DF LEONG, HW LIU, CL Department of Computer Science University of Illinois Urbana-Champaign Urbana IL USA

A simulated-annealing programmable-logic array (PLA) folding algorithm is presented for simple as well as multiple-column folding. Experimental results indicate that the algorithm performs very well. In many test problems, the results are superior to those produced by the well-known heuristic algorithm of G. De Micheli and A. Sangiovanni-Vincentelli (1983). It is also shown that the algorithm can be extended to handle constrained folding.

关键词： programmable logic arrays Simulated annealing Input variables logic arrays Testing Process design Heuristic algorithms Computational modeling Circuit simulation Continuous wavelet transforms

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A NEW APPROACH TO THE DESIGN OF BUILT-IN SELF-TESTING PLAS FOR HIGH FAULT COVERAGE

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1988年第1期7卷 60-67页

作者： UPADHYAYA, SJ SALUJA, KK UNIV WISCONSIN DEPT ELECT & COMP ENGNMADISONWI 53706

Four critical requirements are identified for the built-in self-testing of programmable logic arrays (BIST PLAs): the test set to test the PLA as well as the output response must be independent of the function of the PLA; the test pattern generator (TPG) and the response evaluator circuits must be simple to keep the extra logic overhead to a minimum; the fault coverage of the PLA must be within acceptable limits; and the speed of the test application must be high. A design that meets all of these goals is proposed. The approach is based on counting crosspoints, as opposed to the conventional parity technique. The TPG and RE circuits are simple and consist of shift registers and counters. The design requires a reorganization of the columns of the PLA on the basis of the number of crosspoints. This design provides extremely high fault coverage: the coverage for multiple faults is higher than that of any BIST design known to the authors, and the single-fault coverage is 100%. The design is simple and can easily be incorporated into existing computer-aided design systems.< >

关键词： Built-in self-test programmable logic arrays Circuit testing logic testing Automatic testing Circuit faults logic circuits Fault diagnosis Test pattern generators Shift registers

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PLATYPUS - A PLA TEST PATTERN GENERATION TOOL

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1986年第4期5卷 633-644页

作者： WEI, RS SANGIOVANNIVINCENTELLI, A Department of Electrical Engineering and Computer Science University of California Berkeley CA USA

PLATypus (PLA Test pattern generation and logic simulation tool) is an efficient tool for large PLA's which is interfaced with other existing PLA tools such as the folding program PLEASURE [12] and the logic minimizer ESPRESSO II-C [11] developed at the University of California at Berkeley. A new algorithm is proposed based on complementation and the tautology check of a logic cover, derived from the PLA personality matrix. Both complementation and tautology check are performed by advanced logic manipulation algorithms used in the logic minimization program ESPRESSO II-C [11]. The algorithm is exact, i.e., every testable crosspoint fault is tested, and maximum fault coverage is guaranteed. A quick preprocess, the biased random test generation, is used followed by the proposed algorithm to achieve the best balance between run time and test-set compactness. The program is refined at various stages by many powerful heuristics in the area of fault processing order, backend fault simulation, "don't-care" bit fixing, and on-the-fly test compaction. Both single stuck-at and crosspoint fault models are supported. PLATYPUS can also be used as a logic simulation tool and redundancy identifier. Test pattern generation has been performed by PLATYPUS on a large number of industrial PLA's.

关键词： programmable logic arrays Test pattern generators logic testing Automatic testing logic arrays Very large scale integration Minimization methods Compaction Power system modeling Redundancy

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Formulation- Properties Versatility of Wood Fiber Biocomposites Based on Polylactide and Polylactide/ Thermoplastic Starch Blends

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POLYMER ENGINEERING AND SCIENCE 2014年第6期54卷 1325-1340页

作者： Mihai, Mihaela Legros, Nathalie Alemdar, Ayse Natl Res Council Canada Quebec City PQ J4B 6Y4 Canada FPInnovat Wood Biomat Dept Quebec City PQ G1P 4R4 Canada

This article discusses the interrelation between formulation, processing, and properties of biocomposites composed of a bioplastic reinforced with wood fibers. Polylactide (PLA) and polylactide/thermoplastic starch blends (PLA/TPS) were used as polymeric matrices. Two grades of PLA, an amorphous and a semicrystalline one, were studied. TPS content in the PLA/TPS blends was set at 30, 50, and 70 wt%. Two types of wood fiber were selected, a hardwood (HW) and a softwood (SW), to investigate the effect of the fiber type on the biocomposite properties. Finally, the impact of different additives on biocomposite properties was studied with the purpose to enhance the bioplastic/wood fiber adhesion and, therefore, the final mechanical performance. The biocomposites containing 30 wt% of wood fibers were obtained by twin-screw extrusion. The properties of the biocomposites are described in terms of morphology, thermal, rheological, and mechanical properties. Furthermore, the biocomposites were tested for humidity and water absorption and biodegradability. An almost 100% increase in elastic modulus and 25% in tensile strength were observed for PLA/wood fiber biocomposite with the best compatibilization strategy used. The presence of the TPS in the biocomposites at 30 and 50 wt% maintained the tensile strength higher or at least equal as for the virgin PLA. These superior tensile results were due to the inherent affinity between the matrices and wood fibers improved by the addition of a combination of coupling and a branching agent. In addition to their outstanding mechanical performance, the biocomposites showed high biodegradation within 60 days. POLYM. ENG. SCI., 54:1325-1340, 2014. (c) Her Majesty the Queen in Right of Canada 2013

关键词： Wood fibres Fiber programmable logic arrays Blends BIOCOMPOSITE Polylactides Tensile Strength transaction processing system

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MUSE - A MULTILEVEL SYMBOLIC ENCODING ALGORITHM FOR STATE ASSIGNMENT

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1991年第1期10卷 28-38页

作者： DU, XJ HACHTEL, G LIN, B NEWTON, AR UNIV CALIF BERKELEY DEPT ELECT ENGN & COMP SCIBERKELEYCA 94720

A novel state assignment algorithm, called MUSE (multilevel symbolic encoding), for the encoding of FSMs (finite state machines) targeted for multilevel implementation is presented. Novel methods are discussed for the computation of state pair costs that are based onmultilevel algebraic structures derived from the one hot encoded state machine by purely algebraic techniques. Both Boolean (distance-1 MERGE and consensus) and algebraic (SUB-EXPRESSION EXTRACTION and CO-KERNEL EXTRACTION) operations are used to calculate the encoding affinity of state pairs, and account for face embedding constraints as well. Both heuristic and simulated annealing encoding techniques are used.< >

关键词： Encoding State estimation Costs programmable logic arrays Design automation Automata Simulated annealing Computer science Minimization methods

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Stimulation by Pearl of Mineralization and Biocompatibility of PLA

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ADVANCED ENGINEERING MATERIALS 2015年第11期17卷 1691-1697页

作者： Dai, Jiamu Bai, Jingjing Jin, Junhong Yang, Shenglin Li, Guang Donghua Univ State Key Lab Modificat Chem Fibers & Polymer Mat Shanghai 201620 Peoples R China

Biodegradable materials used for bone repair have recently gained greater attention. The improvement of the mineralization rate and the biocompatibility of are critical. In this study, natural pearl powder is added to polylactic acid (PLA) to accelerate both two properties of PLA. The results show that the amount of hydroxyapatite (HA) deposition on PLA/pearl composite increased with pearl content increasing up to 15wt%, especially at the beginning of mineralization. The HA is a poorly crystallized calcium-deficient type as indicated by FTIR, EDS, and XRD. Osteoblasts are used to evaluate cellular proliferation. An MTT assay reveals that composites are non-toxic and show better proliferation than pristine PLA. It is concluded that PLA/pearl could be more appropriate for bone repairs than PLA.

关键词： pearls bone fusions biodegradable materials Composites programmable logic arrays Stimuli Mineralization PEARL ESSENCE Stimulation mineralization rate biomaterial compatibility poly(lactic acid)

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AN INTEGRATED MODULAR AND STANDARD CELL VLSI DESIGN APPROACH

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1985年第1期20卷 407-412页

作者： KASAI, R FUKAMI, K TANSHO, K KITAZAWA, H HORIGUCHI, S Atsugi Electrical Communication Laboratories Nippon Telegraph and Telephone Public Corporation Atsugi Japan

An advanced design method integrating different design approaches is proposed which can attain an optimized chip design within an acceptable turnaround time (TAT). logic VLSI networks can be generally partitioned into data path logic, control logic, and on-chip memories. The data path logic is primarily realized by using repeatable structured general purpose function blocks, while the control logic is designed using standard cells or programmable logic arrays (PLA's). A cell library and powerful CAD programs are utilized to shorten the TAT. A CMOS 16-bit micro-computer is designed with this approach and compared with a fully automated standard cell chip. A gate density improvement of 30 percent is observed. A design effort of only 20 man-months is achieved.

关键词： Very large scale integration programmable logic arrays CMOS logic circuits logic design programmable control Design methodology Design optimization Chip scale packaging Network-on-a-chip Automatic control

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APPLICATION OF A MICROPROCESSOR BASED SOLID-STATE programmable logic SYSTEM FOR CONTROL OF CLASS 1E COMPONENTS AND DEVICES

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IEEE TRANSACTIONS ON ENERGY CONVERSION 1986年第2期1卷 30-35页

作者： REBBAPRAGADA, RV HICKS, D GARRITY, GE CRBRP PROJECT OAK RIDGETN 37831 CONSOLIDATED CONTROLS CORP BETHELCT 06801

The paper discusses the microprocessor based Solid State programmable logic System (SSPLS) designed for the Clinch River Breeder Reactor Plant (CRBRP) which was terminated in December 1983 by U.S. Congress. Even though procurement of equipment did not take place, the topics discussed here reflect the advanced engineering and design completion (85 percent) on the project and the authors feel that the information presented reflects worthwhile experience associated with the implementation of the state-of-the-art technology and may benefit future designs as well as the industry in general. Topics presented include discussion on design description and hardware, programming, verification and validation, licensing concerns and requirements on reliability and maintainability. The paper describes licensing interaction with the Nuclear Regulatory Commission (NRC) Staff at the construction permit stage and outlines additional details that would be needed at an operating license permit stage.

关键词： Microprocessors Solid state circuits logic devices programmable logic arrays programmable logic devices programmable control Control systems Licenses logic design Rivers

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Model-Driven Learning for Physical Layer Authentication in Dynamic Environments

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IEEE COMMUNICATIONS LETTERS 2024年第3期28卷 572-576页

作者： Han, Jingyuan Li, Yuxuan Liu, Gang Ma, Jingye Zhou, Yi Fang, He Wu, Xuewen China Telecom Res Inst Shanghai 200120 Peoples R China Soochow Univ Sch Elect & Informat Engn Suzhou 215031 Peoples R China Tongji Univ Coll Elect & Informat Engn Shanghai 201804 Peoples R China

This letter investigates the physical layer authentication (PLA) in dynamic environments, where the users have different mobility velocities. The performance of PLA in this scenario suffers from the inaccurate prediction of the channel statement information (CSI) owing to the Doppler shifts and multipath fading. To overcome the difficulty, a model-driven learning algorithm is developed to predict dynamic CSI. Specifically, the Bahdanau Attention Autoencoder (BAAE)-based PLA scheme is proposed to extract relevant channel features and mitigate inter-symbol interference and inter-carrier interference. Compared to existing deep learning-based PLA schemes, the proposed scheme addresses the core factors contributing to poor authentication accuracy at the algorithmic level, rather than brute-force learning from bigger datasets. Experiment results show that the proposed scheme presents more accurate predictions and lower complexity compared with the existing data-driven models across all tested signal noise ratio levels and velocities. Moreover, it is robust to maintain 99.6% authentication accuracy even when the users are moving with high velocities.

关键词： programmable logic arrays Authentication Training Predictive models Feature extraction Computational modeling Wireless communication Physical layer authentication model-driven learning attention mechanisms

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