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Photocurable poly(lactic acid) for use as tissue engineering scaffold

Photocurable poly(lactic acid) for use as tissue engineering...

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Biomedical Engineering International Conference (BMEiCON)

作者： Boriphat Methachan Siriporn Tanodekaew Biomedical Engineering Research Unit National Metal and Materials Technology Center (MTEC) Pathumthani Thailand

Polymers and polymer composites are one of the most interested biomaterials to replace the using of metals and ceramics. The main advantages of the polymer are that they are easier to custom made and they are bioresorbable. Their mechanical properties are unmatched when considered to replace metals or ceramics. A photocurable poly(lactic acid) (PLA) resin was developed in our laboratory for use as a tissue engineering scaffold by means of stereolithography (SLA) technique. The main goal of this work is to improve the mechanical properties of the samples made from the PLA resin. First, PLA resins are synthesized from two different isomers; L-Lactide and D,L- Lactide. Maximum flexural stress of the samples made from both resins is not statically significant but is almost double when compared with commercial bone cements. When L-Lactide resin is sterilized by gamma ray, the sterilization slightly increases both maximum flexural stress and flexural modulus. The degradation of the sterilized samples in 1X PBS at 37°C also improves in terms of mechanical properties. Adding of carbon nanotube functionalized with carboxyl group decreased the mechanical properties of the samples by 35%. From these results, the carbon nanotubes needed to be modified before adding to improve mechanical properties of the photocurable PLA.

关键词： Resins programmable logic arrays Stress Carbon nanotubes Plastics Degradation

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Biodegradable additive manufactured ferroelectret as mechanical sensor

Biodegradable additive manufactured ferroelectret as mechani...

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IEEE SENSORS

作者： Omar Ben Dali Sergey Zhukov Claas Hartman Heinz von Seggern Gerhard M. Sessler Mario Kupnik Measurement and Sensor Technology Group Technical University of Darmstadt Germany Electronic Materials Technical University of Darmstadt Germany Institute for Telecommunications Technology Technical University of Darmstadt Germany

Ferroelectrets are piezoelectric polymers, typically cellular polymer foams that exhibit a large piezoelectric response. In this work, we present a biodegradable 3D printed ferroelectret using Fused Deposition Modeling (FDM). Even though the charging process of the ferroelectret is conducted at room temperature, the printed PLA exhibits good charge stability over 150 days at this temperature. A distinctive feature of the manufactured ferroelectret is that its mechanical properties mainly depend on its geometry, offering the possibility for it to be softer than the printed material itself. In fact, the investigated geometry in this paper exhibits a Young’s modulus of 0.5 kPa for stresses under 1 kPa. An excellent piezoelectric coefficient of 600 pC/N was recorded, which is comparable with the well known polypropylene ferroelectret. The presented ferroelectret is suitable for various mechanical sensor application.

关键词： Mechanical sensors Geometry Solid modeling Temperature Three-dimensional displays programmable logic arrays Stability analysis

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On Optimal Board-Level Routing for FPGA-based logic Emulation

On Optimal Board-Level Routing for FPGA-based Logic Emulatio...

引用

Design Automation Conference

作者： D.F. Wong Wai-Kei Mak Department of Computer Sciences University of Texas at Austin Austin TX

In this paper, we consider a board-level routing problem which is applicable to FPGA-based logic emulation systems such as the Realizer system [3] and the Enterprise Emulation System [5] manufactured by Quickturn Systems. For the case where all nets are two-terminal nets, we present an O(n/sup 2/)-time optimal algorithm where n is the number of nets. Our algorithm guarantees 100% routing completion if the number of inter-chip signal pins on each FPGA chip in the logic emulation system is less than or equal to the number of I/O pins on the chip. Our algorithm is based on iteratively finding Euler circuits in graphs. We also prove that the routing problem with multi-terminal nets is NP-complete.

关键词： Routing Emulation Field programmable gate arrays Pins logic design Design automation Iterative algorithms Digital systems Integrated circuit interconnections programmable logic arrays

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FPGA segmented channel routing using genetic algorithms

FPGA segmented channel routing using genetic algorithms

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Congress on Evolutionary Computation

作者： Lipo Wang Lei Zhou Wen Liu College of Information Engineering Xiangtan University Xiangtan Hunan China School of Electrical and Electronic Engineering Nanyang Technological University Singapore

A genetic algorithm approach for segmented channel routing in field programmable gate arrays (FPGA's) is presented in this paper. The FPGA segmented channel routing problem (FSCRP) is formulated as a special case of a matrix row matching problem which is known to be NP-complete. The goal of FSCRPS is to find a conflict-free net assignment in the tracks within the channel with the minimum routing cost. Simulations on 30 benchmark instances show that GA is able to obtain better solutions compared to the gradual neural network (GNN) approach.

关键词： Field programmable gate arrays Routing Genetic algorithms Switches Power capacitors Costs Pins Neural networks programmable logic arrays Very large scale integration

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A Seamless Handover Mechanism For IEEE 802.16e Systems

A Seamless Handover Mechanism For IEEE 802.16e Systems

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International Conference on Communication Technology (ICCT)

作者： Peng Li XiaoXin Yi Yan Pan Institute of Communication Engineering People''s Liberation Army University of Science and Technology Nanjing Jiangsu China

In this paper, we developed a loss-free handover scheme for IEEE802.16e based wireless broadband access networks. Minimized the handover delay and eliminates packet losses during handover. By integrating MAC and network layer handovers efficiently. Results of simulations show that it achieves loss-free packet delivery without packet duplication and increases system throughput significantly.

关键词： programmable logic arrays Spine Frequency synchronization Wireless LAN Delay Throughput Bandwidth Land mobile radio cellular systems Degradation Mobile radio mobility management

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A new acquisition method for PN code acquisition with large frequency offset

A new acquisition method for PN code acquisition with large ...

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International Symposium on Communications and Information Technologies (ISCIT)

作者： Jian Cheng WenMing Zhu Bo Liu GuangXia Li Satellite Communication Research Center Institute of Communication Engineering of PLAUST Nanjing China Postgraduate Team 4 PLA University of Engineering and Technology Nanjing China

The paper presents a new code acquisition method for usage in DSSS communication system with large frequency offset. A serial correlator combined with decimation filters, which outputs are then fed into FFT process. By using the FFT technique, the search over the frequency uncertainty can be omitted and the usage of decimation filter can improve frequency resolution significantly. The performance in terms of mean acquisition time and SNR is shown to be better over traditional serial acquisition techniques. The hardware complexity is also reduced greatly at the same time.

关键词： Correlators Spread spectrum communication Hardware Matched filters Frequency synchronization Integrated circuit noise Gaussian noise Phase noise Pulse modulation programmable logic arrays

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A Hierarchical Approach to Sign Recognition

A Hierarchical Approach to Sign Recognition

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IEEE Workshop on Applications of Computer Vision (WACV)

作者： Piyanuch Silapachote Allen Hanson Richard Weiss Department of Computer Science University of Massachusetts Amherst Amherst MA USA School of Cognitive Science Hampshire College Amherst MA USA

Sighted individuals draw a significant amount of information from signs but this information is denied to the visually impaired. VIDI is an evolving system for detecting and recognizing signs in the environment and voice synthesizing their textual contents. The wide variety of signs commonly encountered and the uncontrolled nature of the real world add significant complexity to the problem. VIDI treats the recognition problem as one of matching an unknown sign image, obtained from the detection component as a hypothesized sign, to a database of known signs. A color based support vector machine classifier coarsely picks a group of sign classes that are the most likely matches to the query. A finer retrieval technique employing corners and shape contexts ranks the hypothesized sign classes and verifies whether or not the top ranked class is the true class of the query. The database includes a set of real images with a wide variety of sign classes, each containing multiple signs exhibiting not only illumination differences, but also rotational variations. Tested on over 1,200 images, our system correctly recognizes and identifies the sign class of a query, achieving a 94.75% accuracy.

关键词： Shape Image recognition Roads Speech recognition Image databases Support vector machines Support vector machine classification Neural networks Computer science programmable logic arrays

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Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)

Built-in self-test of logic blocks in FPGAs (Finally, a free...

引用

VLSI Test Symposium

作者： C. Stroud S. Konala Ping Chen M. Abramovici Department of Electrical Engineering University of Kentucky USA Cirrus Logic Inc. Fremont CA USA Lucent Technologies Inc. Murray Hill NJ USA

We present a new approach for Field programmable Gate Array (FPGA) testing that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test. As a result, BIST is achieved without any area overhead or performance penalties to the system function implemented by the FPGA. Our approach is applicable to all levels of testing, achieves maximal fault coverage, and all tests are applied at-speed. We describe the BIST architecture used to test all the programmable logic blocks in an FPGA and the configurations required to implement our approach using a commercial FPGA. We also discuss implementation problems caused by CAD tool limitations and limited architectural resources, and we describe techniques which overcome these limitations.

关键词： Built-in self-test Field programmable gate arrays Circuit testing logic testing System testing Circuit faults programmable logic arrays logic devices Automatic testing logic circuits

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Self-Actuating 3D Printed Packaging for Deployable Antennas

Self-Actuating 3D Printed Packaging for Deployable Antennas

引用

Electronic Components and Technology Conference (ECTC)

作者： Ryan Bahr Abdullah Nauroze Wenjing Su M. M. Tentzeris Electrical and Computer Engineering Georgia Institute of Technology Atlanta USA

In this paper we demonstrate the ability to use low-cost 3D printers to manufacture an ambulatory antenna at Ka bands with shape memory polymers to be used in an origami array. A focus on the manufacturing process and limitations is discussed. The antenna is metalized on the 3D printed dielectric substrate (polylactic acid) using direct print additive manufacturing to deposit a single part silver epoxy paste using a 152.4 μm syringe needle. After folding the substrate in a space saving state, a 60 °C heat source returns the shape memory polymer back to its printed permanently stored state. This demonstrates the possibilities of integrating shape memory polymers into packaging for the first time, while enabling future applications with heatsinks, origami meta-materials, and additional reactive and compact structures.

关键词： Shape Three-dimensional displays Three-dimensional printing Printers Substrates Plastics programmable logic arrays

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A PLD Architecture for High Performance Computing

A PLD Architecture for High Performance Computing

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International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems

作者： Naoki Hirakawa Masanori Yoshihara Kazuya Tanigawa Tetsuo Hironaka Masayuki Sato Graduated School of Information Sciences Hiroshima City University Hiroshima Japan Graduated School of Engineering Tokyo Metropolitan University Tokyo Japan

ISBN: (纸本)9781424464654

In recent years, Field programmable Gate arrays (FPGAs) have been used for High Performance Computing (HPC). Because there is a significantly difference between configuration speed of FPGA and execution speed of Central Processing Unit (CPU), the difference causes performance degradation. To resolve of this problem, we proposed MPLD as a new programmable logic Device (PLD) architecture with high speed reconfiguration. The merits of the MPLD in HPC are high speed configuration and easy partial *** is achieved by the configuration method which is same as write memory access of conventional parallel memory. In this paper, we describe the problems of FPGA on using it in HPC, and present the MPLD architecture which solves the problems. Some evaluation results of the prototype MPLD chip which implemented by using five metal layers ROHM 0.18¿m CMOS technology are also presented. As results, memory capacity of the prototype MPLD was 49152bit, and the core area was 1767.54 × 1690.96¿m2 and the number of metal layers used for wiring was three. The achieved configuration time is about 6.6¿sec for whole prototype MPLD. The configuration speed of the prototype MPLD is about 11.7 times higher than AS configuration used for Altera FPGAs.

关键词： Computer architecture High performance computing Field programmable gate arrays Prototypes Central Processing Unit CMOS technology programmable logic arrays Degradation programmable logic devices Wiring

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