TOPOLOGIZER is an expert system for the design of CMOS cells. It automatically generates a symbolic layout given a transistor connection list and a description of the boundary assignment of external cell connections. ...
详细信息
TOPOLOGIZER is an expert system for the design of CMOS cells. It automatically generates a symbolic layout given a transistor connection list and a description of the boundary assignment of external cell connections. As part of an overall approach to silicon compilation it uses expert designer specified heuristics to perform the difficult task of converting a structural description (schematic) into a physical description that maintains some notion of structured layout principles.
LEACH is a hierarchy routing protocol for WSN (wireless sensor networks), which is superior to direct communication protocol, minimum-transmission-energy protocol and static clustering protocol. However, LEACH itself ...
详细信息
LEACH is a hierarchy routing protocol for WSN (wireless sensor networks), which is superior to direct communication protocol, minimum-transmission-energy protocol and static clustering protocol. However, LEACH itself has some defects. In this paper LEACH-TM introduces the concept of trust, designs the cluster-head adjusting procedure and establishes multi-path with cluster-heads acting as routers. The simulation illustrates that LEACH-TM makes much progress in the reliability of data transmission, the distribution of cluster heads and the lifetime of networks.
The paper describes a specific method for designing self-checking checkers for m-out-of-n codes. The method is oriented to the field programmable gate arrays technology and is based on decomposing the sum-of-minterms ...
详细信息
The paper describes a specific method for designing self-checking checkers for m-out-of-n codes. The method is oriented to the field programmable gate arrays technology and is based on decomposing the sum-of-minterms corresponding to an m-out-of-n code. The self-testing property of the proposed checker is proven for a set of multiple stuck-at faults at input and output poles of a logic cell. An estimated complexity of obtained m-out-of-n checker demonstrates high efficiency of the proposed method.
To reduce the cost of abundant mobile sensors deployed in unknown environment, a target-oriented self-deployment algorithm (TSA) based on attracting force line is proposed. By designing the attracting force line and c...
详细信息
To reduce the cost of abundant mobile sensors deployed in unknown environment, a target-oriented self-deployment algorithm (TSA) based on attracting force line is proposed. By designing the attracting force line and constructing virtual attracting force and repulsive force, the paths between sink and targets are set up automatically. Simulation results show that the proposed algorithm compared to similar methods achieves shorter average moving distance with shorter maximum moving distance and shortens the deployment time.
This paper discusses a powerful experimental technique that makes it possible to examine the effect of logic block attributes on the block area density. The logic block is XOR-AND based, and five unique attributes wer...
详细信息
This paper discusses a powerful experimental technique that makes it possible to examine the effect of logic block attributes on the block area density. The logic block is XOR-AND based, and five unique attributes were investigated. The experiment consisted of several iterations in which benchmark circuits were mapped on to various blocks, each varying in some attribute. Results are plotted on to a response contour map, indicating a point of maximum area density. The results have shown that inverting primary inputs to AND gates of the function structure is insignificant. In addition results indicate that two level function structures with an XOR output gate are able to contain logic in the smallest physical area.< >
The design of self-checking circuits through output encoding finds a bottleneck in the realization of the network so that each fault produces only detectable errors. New conditions are defined for identifying the set ...
详细信息
The design of self-checking circuits through output encoding finds a bottleneck in the realization of the network so that each fault produces only detectable errors. New conditions are defined for identifying the set of gates that, if faulty, cause undetectable errors, taking into account AUED codes (Berger and m-out-of-n) and the Parity code, for a reduction of the re-design of the circuit and, consequently, of costs.
A structured design procedure for systems integration sequential logic which is to be implemented on programmablelogic controllers is presented. The procedure offers the advantages of producing intrinsically robust s...
详细信息
A structured design procedure for systems integration sequential logic which is to be implemented on programmablelogic controllers is presented. The procedure offers the advantages of producing intrinsically robust software which is very easy to understand and to modify as systems requirements change. The approach takes advantage of the sequential nature nature of processors to assure that the order of solution of the sequential logic equations is consistent with maximum speed and instantaneous correctness of the output states. The authors present examples of the basic elements of the structured design procedure from which any type of system integration can be implemented. An example is given of an industrial die cast molding machine system.< >
This paper examines the use of compact FPGA-based configurable processors as an alternative to ever-higher powered general purpose CPUs. It describes sample applications in which even a very simple configurable proces...
详细信息
This paper examines the use of compact FPGA-based configurable processors as an alternative to ever-higher powered general purpose CPUs. It describes sample applications in which even a very simple configurable processor outperforms all but very fast general purpose CPUs. Performance data is given for DES encryption, labeling objects in black-and-white images, and LZW decompression. In particular, the design of the labeling co-processor is presented.
A method for solving the technology mapping problem for field-programmable gate arrays that is based on the genetic algorithm is presented. The genetic algorithm simultaneously optimizes a set of solutions, which make...
详细信息
A method for solving the technology mapping problem for field-programmable gate arrays that is based on the genetic algorithm is presented. The genetic algorithm simultaneously optimizes a set of solutions, which makes it a very powerful optimization technique. However, due to the highly constrained search spaces for design automation problems, the application of the genetic algorithm is not straightforward. It is shown that this limitation can be overcome by enhancing the genetic search appropriately. The performance of the enhanced genetic search is demonstrated through experimental results for the technology mapping problem.< >
暂无评论