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检索条件"主题词=Programmable Logic Arrays"

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Improved method of decoy state quantum key distribution based with HPCS sources

Improved method of decoy state quantum key distribution base...

引用

International Conference on E-Business and E-Government (ICEE)

作者： Shun-Jin Li Yu Guan Min He Institute of Sciences People''s Liberation Army University of Science and Technology Nanjing China

ISBN: (纸本)9781424486915

Based on the heralded pair-coherent states sources, the Vacuum+Weak decoy state protocol focused on BB84 is presented. Combining the passive decoy state method and the active decoy state method, we use the triggered and nontriggered components to estimate the fraction of single-photon counts and quantum bit-error rate of single-photon and to generate the secure key. From the simulation results of the final key rate over the distance, which shows that our method improve the QKD performance and obtain higher key generation rate than that of the active decoy states method.

关键词： Elementary particle vacuum Cryptography Optical fiber communication Simulation programmable logic arrays Computers Telecommunications

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Evolutional design of small antennas for passive UHF-band RFID

Evolutional design of small antennas for passive UHF-band RF...

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Biennial Institute of Electrical and Electronics Engineers Conference on Electomagnetic Field Computation

作者： Hidetoshi Makimura Yuta Watanabe Kota Watanabe Hajime Igarashi Graduate School of Information Science and Technology Hokkaido University

ISBN: (纸本)9781424470594

This paper presents optimal design of antennas for passive IC tags used in UHF-band radio frequency identification. To improve the performance of IC tags, the shape of the meander line antennas and planar lattice antennas are optimized using the genetic algorithm. In the optimization process, the objective function includes the terms relevant to the antenna size, gain and input impedance. The characteristics of the antennas printed on a dielectric substrate are evaluated using the moment method. The optimization results in desirable input impedance for impedance matching and miniaturizing.

关键词： Radiofrequency identification Passive RFID tags Dipole antennas Shape programmable logic arrays Lattices Dielectric substrates Impedance matching Optimization methods Genetic algorithms

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The study of the instruction strategy on armored equipment major courses based on virtual reality technology

The study of the instruction strategy on armored equipment m...

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International Conference on Multimedia Technology

作者： Jian Zhang Tao Huang Kuishan Zhang Bin Li Control Engineering Department Armored Force Engineering Institute Beijing China 1st Research Room 63961 Unit People''s Liberation Army Beijing China

ISBN: (纸本)9781612847719

Aiming at the teaching problems of major courses on armored equipment, this article sets forth the instruction strategy, which sets up the instruction situation referencing the usual training task in armored and mechanized army based on desktop virtual reality system to improve the learning enthusiasm of students. The instruction strategy is executed through 'subject' combined with 'question', and is designed on three aspects: visual cognition design, interactivity design and virtual situation learning, which are aligned with the desktop virtual reality system.

关键词： Education Virtual reality Materials Control engineering programmable logic arrays IP networks Visualization

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Exploring in the teaching mode of intensive teaching and independent learning

Exploring in the teaching mode of intensive teaching and ind...

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International Conference on E-Business and E-Government (ICEE)

作者： Lirong Ma Xuefeng Li Liwei Liu Educational Technology Centre of Flight Fundamental Training Base Aviation University슠of Air슠Force ChangChun China Flight Fundamental Training Base Aviation University슠of Air슠Force ChangChun China College of Computer Science and Engineering Changchun University of Technology Changchun China

ISBN: (纸本)9781424486915

A completely new teaching mode emerges encompassing Intensive Teaching and Independent Learning as a result of optimizing education resources with advanced education technology in info-net environment. The new teaching mode in info-net environment is set up in this paper by means of analyzing and explaining concepts related, mutual relations and functions.

关键词： Publishing Training Management information systems programmable logic arrays Computers Multimedia communication

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Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy

Power, Delay and Yield Analysis of BIST/BISR PLAs Using Colu...

引用

8th International Symposium on Quality Electronic Design (ISQED 2007)

作者： Uthman Alsaiari Resve Saleh Electrical and Computer Engineering Department University of British Columbia Vancouver Canada

As the number of transistors on a chip begins to exceed 1 billion, it will be mandatory to use a portion of the transistors for the purposes of Built-in-Self-Test (BIST) and Built-in-Self-Repair (BISR) as part of the supporting circuitry. However, this will require the use of structured logic, such as programmable logic arrays (PLAs) or structured ASIC. In this paper, we select the fastest and lowest energy PLA design to date and combine it with a block duplication strategy to construct a BIST/BISR PLA in order to establish a reference design. Then, we introduce a PLA redundancy in the form of spare columns and carry out a yield analysis. The results of the yield analysis suggest that using duplication for BIST/BISR is better suited for small PLAs while using spares is more suitable for larger PLAs. The spares needed are determined by several factors including target yield, area, power and delay.

关键词： Delay Built-in self-test programmable logic arrays Redundancy Circuit testing Automatic testing logic testing Integrated circuit yield Circuit faults Semiconductor device manufacture

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Performance Enhancement and High-Level Specification of a Pipelined Processor in programmable logic

Performance Enhancement and High-Level Specification of a Pi...

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IEEE North-East Workshop on Circuits and Systems (IEEE-MWCAS'07)

作者： Naraig Manjikian Jonathan Roth Department of Electrical and Computer Engineering Queen''s University Kingston ONT Canada

This paper describes the performance enhancement of a custom pipelined processor in programmable logic, and the description of the enhanced processor with the higher-level specification syntax of a custom software tool for system implementation in hardware. Faster operation of the processor is enabled with a revised clocking scheme for the embedded memory blocks that are used for the register file and the caches. A higher-level implementation of the enhanced processor is specified with a custom software tool called QUI{sup}2VER (Queen's University Interface Integrator in VHDL for Education and Research) that generates VHDL output. Synthesis results obtained with Altera Quartus II for a Stratix chip characterize the modest overhead for the datapath modifications to support the revised clocking scheme in the enhanced processor datapath. Results from timing analysis indicate an increase in the processor clock frequency by 76% relative to the previous implementation.

关键词： programmable logic arrays programmable logic devices Clocks Registers logic devices Prototypes Pipelines Software tools Hardware Timing

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Incremental-best-relay selection scheme in coded cooperative networks

Incremental-best-relay selection scheme in coded cooperative...

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International Conference on E-Business and E-Government (ICEE)

作者： Chunming Shen Yuanyuan Gao Yalong Zhang Mingxi Guo Institute of Communications Engineering People''s Liberation Army University of Science and Technology Nanjing China

ISBN: (纸本)9781424486915

Incremental relaying is introduced to the multi-nodes coded cooperative system. The Incremental-Best-Relay selection scheme in coded cooperative networks is proposed based on opportunistic relaying selection strategy. The outage probability and average spectral efficiency are analyzed and simulated. Simulation results show that the proposed scheme can achieve higher average spectral efficiency while keep the same outage probability as opportunistic relaying-coded cooperation, and an optimal average spectral efficiency also can be found as the average ratio of signal to noise (SNR) is fixed.

关键词： Relays Time division multiple access Wireless communication Signal to noise ratio Simulation Spread spectrum communication programmable logic arrays

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Cluster-level parameters at 5.25 GHz indoor-to-outdoor and outdoor-to-indoor MIMO radio channels

Cluster-level parameters at 5.25 GHz indoor-to-outdoor and o...

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16th IST Mobile and Wireless Communications, vol.2

作者： Lassi Hentila Mikko Alatossava Nicolai Czink Pekka Kyosti Elektrobit Limited Oulu Finland 4G Lab / Centre for Wireless Communications University of Oulu Finland Telecommunications Research Center Vienna Vienna Austria Institut für Nachrichtentechnik und Hochfrequenztechnik Technische Universität Wien Vienna Austria

This paper describes cluster-level results of indoor-to-outdoor and outdoor-to-indoor double-directional MIMO radio channel measurements carried out at 5.25 GHz. The measurements were performed using a wideband multi-antenna radio channel sounder. Using a set of several thousands of snapshots at the two reciprocal environments, we provide a useful insight into the channel for further channel modelling and channel simulations. We discuss the cluster azimuth spread, cluster delay spread, inter-cluster shadowing, number of clusters per snapshot, number of paths within the cluster, cluster birth rate and cluster lifetime. These parameters are presented for different scenarios by their statistical distributions, and also by their cross-correlation. The results show that both outdoor-to-indoor and indoor-to-outdoor scenarios behave very similar, so we suggest to merge these two cases.

关键词： MIMO Azimuth Delay Frequency Transmitting antennas Wireless communication Wideband programmable logic arrays Costs Antenna measurements

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On the complexity of switch programming in fault-tolerant configurable chips

On the complexity of switch programming in fault-tolerant co...

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IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

作者： W. Shi K. Kumar F. Lombardi Computer Science University of North Texas Denton TX USA Electrical & Computer Engineering Northeastern University Boston MA USA

ISBN: (纸本)0769507190

Given a programmable chip (such as a WSI systolic array, or a field programmable gate array (FPGA)) made of equally-like configurable logic blocks (cells), the problem of programming the interconnect resources (consisting of switches) has been well studied in the literature. This process can be used for fault tolerance by logically reconfiguring the fault free cells of the array into a new array as well as to customize the FPGA by configuring it to perform the desired functions. Once the desired logical configuration has been achieved (as in the presence of faulty cells), the (programmable) switches in the interconnect resources of the array must be programmed to implement the target topology on the physical array. In this paper, we study the problem of minimizing the programming time (or cost) required for implementing this step. We show that current techniques are not likely to lead to cost optimal polynomial time algorithms, because the underlying covering problems are NPC-complete in the strong sense. The NPC-completeness is also extended to grid arrays.

关键词： Switches Fault tolerance programmable logic arrays Field programmable gate arrays logic programming logic arrays Systolic arrays Reconfigurable logic Topology Costs

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Reconfigurable magnetologic computing using MRAM cells

Reconfigurable magnetologic computing using MRAM cells

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2007 International Conference on Electromagnetics in Advanced Applications (ICEAA 2007), vol.2

作者： A. Ney Experimentalphysik Universität Duisburg-Essen Duisburg Germany

A simple hardware concept for a programmable logic element based on a single magnetic random access memory (MRAM) cell is presented. It combines the inherent advantage of a non-volatile output with flexible functionality which has to be selected at run-time. A single MRAM cell can represent one out of up to ten logic functions, among them the four elementary functions AND, OR, NAND and NOR and the two more complex functions XOR and XNOR if bipolar currents are used. Based on recent developments of the MRAM technology, which uses the toggled switching mode, alternative concepts for real MRAM devices will be discussed. As a first application example, which takes advantage of the reprogrammability and non-volatility of the logic elements, a compact design of a magnetologic full adder is presented.

关键词： Hardware Reconfigurable logic programmable logic arrays programmable logic devices Random access memory Nonvolatile memory Runtime logic functions logic devices logic design

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