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检索条件"主题词=Programmable Logic Arrays"

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Analysis of structural mechanics of solid microneedle using COMSOL software

Analysis of structural mechanics of solid microneedle using ...

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International Conference on Innovations in Information,Embedded and Communication Systems (ICIIECS)

作者： Urvi Kanakaraj Tshewang Lhaden Karthik Raj V. Department of Biomedical Engineering SRM University Chennai India

Microneedles are currently being extensively researched for therapeutic and diagnostic applications, as they are painless, cheaper than conventional needles, and reduce risk of infection. In this paper, we have selected 10 materials for solid microneedle and have performed the structural analysis of each material using COMSOL Multiphysics 4.3. The study was based on the factors affecting microneedle strength such as buckling and bending forces. The result indicated that the microneedle made of Silicon carbide was superior to the other selected materials and while considering the property of biodegradability for the same study, Silk was preferred. PLA and Polycarbonate experienced buckling and thus were not preferred from the selected materials.

关键词： Force Skin Needles Stress Silicon carbide programmable logic arrays Drugs

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Statistical behavioral modeling for A/D-converters

Statistical behavioral modeling for A/D-converters

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： G. Van der Plas J. Vandenbussche W. Verhaegen G. Gielen W. Sansen Department of Electrical Engineering ESAT-MICAS Katholieke Universiteit Leuven Heverlee Belgium National Fund for Scientific Research Belgium

An automated method to derive the statistical parameters of the building blocks of A/D-converters is presented. This method is applied to an 8-bit full flash A/D-converter. The statistical model is used to simulate INL and DNL and explore statistical effects that cannot be captured in closed expressions. A speedup in simulation times of over 100 is reported compared to device-level simulations.

关键词： Preamplifiers Energy consumption Voltage control Clocks programmable logic arrays System-level design Delay Semiconductor device modeling Parameter extraction Frequency conversion

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A fine-grain Phased logic CPU

A fine-grain Phased Logic CPU

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IEEE Computer Society Annual Symposium on VLSI

作者： R.B. Reese M.A. Thornton C. Traver Mississippi State University USA Southern Methodist University USA Union College USA

A five-stage pipelined CPU based on the MIPs ISA is mapped to a self-timed logic family known as Phased logic (PL). The mapping is performed automatically from a netlist of D-Flip-Flops and 4-input Lookup Tables (LUT4s) to a netlist of Phased logic gates. Each PL gate implements a 4-input Lookup Table in addition to control logic required for the PL control scheme. PL offers a speedup technique known as Early Evaluation that can be used to boost performance at the cost of additional PL gates. Several different PL gate-level implementations are produced to explore different architectural tradeoffs using early evaluation. Simulations run for five benchmark programs show an average speedup of 1.48 over the clocked netlist at the cost of 17% additional PL gates.

关键词： programmable logic devices programmable logic arrays Clocks logic design Application specific integrated circuits Costs Design methodology logic devices Table lookup Automatic control

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Keynote: Probabilistic Programming With Coordination and Compensation

Keynote: Probabilistic Programming With Coordination and Com...

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International Conference on Secure System Integration and Reliability Improvement, SSIRI

作者： Ji-Feng He Shanghai Key Lab. of Trustworthy Comput. East China Normal Univ. Shanghai China

Failure is the typical phenomena of the execution of long-running transactions. To accommodate the random features of Internet-based computing we extend the Guarded Command Language by addition of probabilistic choice and coordination combinators. This paper deals with rollback and compensation mechanisms of the language by providing a probabilistic model. We also discuss algebraic properties of the new combinators, and show the completeness of the algebraic system by show how to convert programs to normal forms.

关键词： Helium Tellurium Content addressable storage Software engineering Laboratories Fellows NIST programmable logic arrays Network address translation

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A decoder-based switch box to mitigate soft errors in SRAM-based FPGAs 10

A decoder-based switch box to mitigate soft errors in SRAM-b...

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Asia and South Pacific Design Automation Conference

作者： Hassan Ebrahimi Morteza Saheb Zamani Hamid R. Zarandi Department of Computer Engineering Amirkabir University of Technology슠 Tehran Iran

ISBN: (纸本)9781605588377

This paper proposes a new switch box architecture in SRAM-based FPGAs to mitigate soft error effects. In this switch box architecture, the number of SRAM bits required for programming switch box is reduced to 67% without any impact on routing capability of the switch box. This architecture does not require any modification of the existing placement and routing algorithms. The architecture was evaluated based on several MCNC benchmarks using VPR tool. The experimental results show that this architecture decreases the susceptibility of switch boxes to SEUs about 20% on average compared to the traditional ones.

关键词： Switches Decoding Field programmable gate arrays Routing Single event upset Single event transient logic devices programmable logic arrays Pins Wire

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An approach to general videogame evaluation and automatic generation using a description language

An approach to general videogame evaluation and automatic ge...

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IEEE Symposium on Computational Intelligence and Games, CIG

作者： Chong-U Lim D. Fox Harrell Computer Science & Artificial Intelligence Laboratory Massachusetts Institute of Technology Cambridge Massachusetts

In this paper, we present an approach for automated evaluation and generation of videogames made with PuzzleScript, a description-based scripting language for authoring games, which was created by game designer Stephen Lavelle [1]. We have developed a system that automatically discovers solutions for a multitude of videogames that each possess different game mechanics, rules, level designs, and win conditions. In our approach, we first developed a set of general level state heuristics, which estimates how close a given game level is to being solved. It is used to adapt the best-first search algorithm to implement a general evaluation approach for PuzzleScript games called GEBestFS. Next, we developed an evolutionary framework that automatically generates novel game mechanics from scratch by evolving game design rulesets and evaluating them using GEBestFS. This was achieved by developing a set of general ruleset heuristics to assess the playability of a game based on its game mechanics. From the results of our approach, we showcase that a description-based language enables the development of general methods for automatically evaluating games authored with it. Additionally, we illustrate how an evolutionary approach can be used together with these methods to to automatically design alternate or novel game mechanics for authored games.

关键词： Games programmable logic arrays

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Boolean decomposition in multi-level logic optimization

Boolean decomposition in multi-level logic optimization

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IEEE International Conference on Computer-Aided Design

作者： S. Devadas A.R. Wang A.R. Newton A. Sangiovanni-Vincentelli Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology USA Department of Electrical Engineering and Computer Science University of California Berkeley USA

Multiple-valued Boolean minimization is proposed as a technique for identifying and extracting good Boolean factors which can be used as strong divisors to minimize the literal count and the area of a multilevel logic network. Given a two-level logic function, a subset of inputs to the function is selected such that the number of good Boolean factors contained in this subset of inputs is large. If the targeted implementation is a set of interconnected PLAs, the different cube combinations given by the subset of inputs are re-encoded to reduce the number of product terms in the logic function. A novel algorithm for the re-encoding is given that is based on the notion of partial satisfaction of constraints. Algorithms have been developed that identify a set of factors which maximally decrease the literal count of the logic network when they are used as strong divisors. Results obtained on several benchmark examples that illustrate the efficacy of the techniques are presented.< >

关键词： Boolean functions programmable logic arrays

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Analysis of substrate noise propagation in a lightly doped substrate [mixed-signal ICs]

Analysis of substrate noise propagation in a lightly doped s...

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European Conference on Solid-State Device Research (ESSDERC)

作者： G. Van der Plas C. Soens G. Vandersteen P. Wambacq S. Donnay Wireless research IMEC Leuven Belgium Vrije Universiteit Brussel Belgium

Analysis and simulation results of substrate noise in mixed-signal ICs on lightly doped substrates are difficult to bring in agreement with measurements, even for very simple structures. In this paper, substrate noise propagation in lightly doped p-type substrates is studied with a simple test structure. Our study reveals that the current flow is multi-dimensional, and that adjacent layout details (such as nwells and metal wires) influence the propagation between two contacts. The analysis has enabled its to match the measured S/sub 21/ propagation with a simulation model from DC (error<8%) up to 10 GHz with an overall error smaller than 3 dB. Insight in simple structures such as the one considered here, is valuable in improving the understanding of substrate noise in lightly doped substrates.

关键词： Optical propagation Wires Testing Electrical resistance measurement Contact resistance Voltage programmable logic arrays Capacitors CMOS process Measurement standards

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Front propagation and level-set approach for geodesic active stereovision

Front propagation and level-set approach for geodesic active...

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IEEE Workshop on Visual Surveillance

作者： R. Deriche C. Bouvin O. Faugeras INRIA Sophia-Antipolis France

Given a weakly calibrated stereo system and a virtual 3D surveillance plane specified by any 3 points given by an external operator we describe a framework for matching complex 2D planar curves lying at the intersection of the 3D surveillance plane and the 3D scene being observed. This important information may then be used to know which parts of the objects being observed are between the stereo system and the virtual 3D surveillance plane, and which parts are behind the 3D virtual surveillance plane i.e. outside a security zone specified around the stereo system. Using an energy minimization based approach, we reformulate this stereo problem as a front propagation problem. The Euler Lagrange equation of the designed energy functional is derived and the flow minimizing the energy is obtained. This original scheme may be viewed as a geodesic active stereo model which basically attract the given curves to the bottom of a potential well corresponding to pixels having similar intensities. Using the level set formulation scheme of Osher and Sethian (1988), complex curves can be matched and topological changes for the evolving curves are naturally managed. The final result is also relatively independent of the curve initialization. Promising experimental results have been obtained on various real images.

关键词： Level set Surveillance Layout Electrical capacitance tomography Active contours Lagrangian functions Equations Identity-based encryption Security programmable logic arrays

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Array-based testing of FPGAs: architecture and complexity

Array-based testing of FPGAs: architecture and complexity

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Annual IEEE International Conference on Innovative Systems in Silicon

作者： W.K. Huang F.J. Meyer F. Lombardi Department of Electronic Engineering Fudan University Shanghai China Department of Computer Science Texas A and M University College Station TX USA

This paper analyzes the architectural and complexity features of the array-based testing technique for field programmable gate arrays (FPGAs). The analysis is pursued using a hybrid (functional/stuck-at) single fault model by considering both the architecture of the configurable logic block (CLB) as well as the whole FPGA. Its evaluation using three commercially available FPGA families by Xilinx is presented in detail; emphasis is given to the different array configurations which permit the observability/controllability requirements of the testing process to satisfy the input/output restrictions (given by the I/O pins) of the FPGA, while still reducing the number of required programming phases.

关键词： Testing Field programmable gate arrays Circuit faults Table lookup programmable logic arrays Phased arrays Decoding Computer architecture logic programming logic arrays

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