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检索条件"主题词=Programmable Logic Arrays"

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Precision requirements for quotient digit selection in high-radix division

Precision requirements for quotient digit selection in high-...

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Asilomar Conference on Signals, Systems & Computers

作者： B. Parhami Department Electrical and Computer Engineering University of California Santa Barbara CA USA

ISBN: (纸本)078037147X

Digit-recurrence binary dividers are sped up via two complementary methods: keeping the partial remainder in carry-save form and selecting quotient digits in a radix higher than 2, usually in redundant form. The redundancy provides some tolerance to imprecision, so that the quotient digits can be selected based on examining truncated versions of the partial remainder and divisor. No closed form formula for the required precision in the partial remainder and divisor, as a function of the quotient digit set and the partial remainder range, is known. We establish upper bounds on the required precision for the partial remainder and divisor. The bounds are tight in the sense that each is only one bit over a well-known lower bound.

关键词： programmable logic arrays Read only memory Redundancy Upper bound Digital arithmetic Convergence Added delay Costs Very large scale integration Circuits

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Enhancements and Applications of a Versatile Software Tool for High-Level Specification of Single-Chip Systems

Enhancements and Applications of a Versatile Software Tool f...

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Canadian Conference on Electrical and Computer Engineering (CCECE)

作者： Naraig Manjikian Cindy Mark Mohanarajah Sinnathamby James Reed Huang Jin Department of Electrical and Computer Engineering Queen's University Kingston ONT Canada

This paper describes several enhancements and various applications of a versatile and extensible software tool called QUI 2 VER to support integration of custom components for research prototyping in programmable logic. From higher-level specifications of components and interconnections in an input file, QUI 2 VER generates an output VHDL file with a desired system configuration. The value of QUI 2 VER stems from how abstract interfaces can be specified in support of component interconnection for system-level configuration. We have enhanced QUI 2 VER with multidimensional array-based and loop-based system specification capabilities. We have included enhanced support for symbolic constants, generic parameters, and arbitrary arithmetic expressions. We have also created a graphical tool to visualize component interface definitions and to support graphical system specification based on such interfaces. We demonstrate our enhancements by using QUI 2 VER to generate systems for single-chip implementation in programmable logic using our own intellectual property, including multidimensional interconnection networks, an extensible embedded processors and a sophisticated cache-coherent multiprocessor based on our own custom pipelined 32-bit processors, split-transaction bus components, and memory components

关键词： Application software Software tools programmable logic arrays programmable logic devices Multidimensional systems Software prototyping Arithmetic Visualization Intellectual property Multiprocessor interconnection networks

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Intelligent multimedia technology and its application in training for operators in Chinese power plants

Intelligent multimedia technology and its application in tra...

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IEEE Region 10 International Conference TENCON

作者： Zhang Jianhua Zhou Qiong Liu Lianguang Li Deheng Pu Ying Luo Yingli North China University of Electric Power Beijing China

Taking into consideration the remarkable diversity of the trainees' knowledge background in Chinese hydro-power plants, we have developed a multimedia intelligent training system (MITS) suitable for various kinds of trainees with different entrance levels and exit targets as well as the duration of the training. In this paper, the teaching strategies adaptable to those trainees. Two presentation methods of some common knowledge points, the inner structure of knowledge points with multiple rules representing the relationship between them as well as the student model and teaching model have been carefully studied so as to form a different learning path for the individual trainee by reasoning on the basis of these rules.

关键词： programmable logic arrays Education Educational institutions Management training Vocational training Power generation Intelligent systems Switches Multimedia systems Knowledge management

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A combination drift chamber/pad chamber for very high readout rates

A combination drift chamber/pad chamber for very high readou...

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IEEE Symposium on Nuclear Science (NSS/MIC)

作者： L. Spiegel T. Alexopoulos L. Antoniazzi M. Arenton C. Ballagh H. Bingham A. Blankman M. Block A. Boden S. Borodin J. Budagov Z.L. Cao G. Cataldi T.Y. Chen K. Clark D. Cline S. Conetti M. Cooper G. Corti B. Cox P. Creti E. Dukes C. Durandet V. Elia A. Erwin L. Fortney V. Golovatyuk E. Gorini F. Grancagnolo M. Haire P. Hanlet M. He G. Introzzi M. Jenkins J. Jennings D. Judd T. Kaeding W. Kononenko W. Kowald A. Lanza K. Lau T. LeCompte G. Liguori J. Lys P. Mazur A. McManus S. Misawa G. Mo C.T. Murphy K. Nelson M. Newcomer M. Panareo S. Ramachandran M. Recagni J. Rhoades J. Rosen J. Segal W. Selove R.P. Smith J. Sun S. Tokar P. Torre J. Trischuk T. Trojak E. Tsyganov L. Turnbull R. VanBerg D. Wagoner C. Wang C. Wei W. Yang N. Yao T. Yao N. Zhang S.N. Zhang B. Zou Fermilab University of Wisconsin USA University of Pavia and INFN Italy University of Virginia USA University of California Berkeley USA University of Pennsylvania USA Northwestern University USA University of California Los Angeles USA JINR Dubna Russia Shandong University China Nanjing University China University of South Alabama USA Vanier College Canada University of Lecce INFN Italy Duke University USA Prairie View A&M University USA University of Houston USA McGill University Canada

Details of the construction of high-rate, mid-sized (1-m*2-m) pad chambers, intended for use in Fermi National Accelerator Laboratory (FNAL) experiment E-771, are described. Each gas volume module represents a chamber doublet: two identical anode wire planes, two transverse strip planes, and two pad planes. Wire signals, from 8-mm square cells, are recorded via TDCs; corresponding stripe and pad image signals are latched. Pad sizes range from 0.8 cm*3.6 cm to 3.2 cm*35 cm. In addition to facilitating pattern recognition, pad signals are also used as inputs to an online, high transverse momentum trigger processor.< >

关键词： Atherosclerosis Anodes Wires Signal processing Pattern recognition programmable logic arrays Educational institutions Laboratories Coordinate measuring machines Mirrors

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Design exploration: extending the bounds of the search space

Design exploration: extending the bounds of the search space

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Congress on Evolutionary Computation

作者： M.A. Beck I.C. Parmee Plymouth Engineering Design Centre University of Plymouth Plymouth UK

It is during conceptual design that neither the problem space nor solution space is fixed and the designers aim is an exploration of a range of possible problem-solution scenarios. Within such a framework the constraints placed upon the initial limits assigned to the design variables are subject to change. Thus this paper presents a multi-population GA approach that allows the search to move outside of its pre-defined limits. Utilising dynamic fitness sharing and directional search techniques sub-populations are encouraged to explore differing high performance and unspecified areas of the search space.

关键词： Design engineering Genetic mutations programmable logic arrays Process design Steady-state Wheels Convergence

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The need of multicast predictive NFS servers for high-speed networks used as parallel multimedia platforms

The need of multicast predictive NFS servers for high-speed ...

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International Conference on Parallel Processing Workshops (ICPPW)

作者： T. Olivares L. Orozco-Barbosa F. Quiles A. Garrido P.J. Garcia Departamento de Informática Universidad Castilla La Mancha Albacete Spain Departamento de Informática Campus Universitario Albacete Spain School of Information Technology and Engineering University of Ottawa Ottawa ON Canada

In this paper we have carried out an experimental study of the I/O latency of a distributed file system over a parallel multimedia platform. Our experimental platform uses NFS (Network File System) to support an application characterized by its high processing and storage requirements. We evaluate the overall system by varying several NFS parameters as well as the underlying network topology and data access patterns. We have also examined the relevance of two other important file management access mechanisms: caching and prefetching. Our experimental results have allowed us to identify the major system parameters affecting the performance of NFS. We then propose the use of a predictive data access mechanisms. Under this mechanism, the file server should detect the similarities among the most recent I/O requests incoming from a set of cooperating clients. Once having identified the access pattern, the file server will be able to multicast the required data even before receiving explicit I/O data requests from the clients. Under this predictive mechanism, the system performance should improve as the number of explicit I/O requests directed to the file server decreases.

关键词： Network servers High-speed networks programmable logic arrays File servers Prefetching Multimedia systems File systems Network topology System performance Access protocols

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A FPGA based modular coincidence arbitrator design for Compton camera with multiple detection blocks

A FPGA based modular coincidence arbitrator design for Compt...

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IEEE Symposium on Nuclear Science (NSS/MIC)

作者： Li Han S.S. Huh N.H. Clinthorne

A field programmable gate array (FPGA) based modular coincidence arbitrator has been designed for the new generation of Compton camera which involves multiple scattering and absorbing detection blocks. Compared with the conventional coincidence trigger generator realized by TAC-SCA modules or separated logic gates, the proposed FPGA design increases the flexibility for coincidence window length adjustment and enables online updates of the look-up-table listing the different combinations of detection blocks that need to be triggered under different inputs. Furthermore, the FPGA design reduces the redevelopment time for modifying detection blocks by using independent function modules. In this design, the coincidence arbitrator is composed of one central control module, several detector coincidence (SD) modules, and one communication module. The central controller is employed to initialize the coincidence window, synchronize the difference detector modules, arbitrate the system coincidence, and trigger the corresponding detection blocks. The SD module, associated with one corresponding detection block, is employed to initialize pulse-delay-timer, delays the pulse generated by the external detector and judges whether that delayed pulse in within the coincidence window. The communication block transmits the states and controllable parameters between the arbitrator and the host PC via the USB port. All the functions of a multiple modular coincidence arbitrator are implemented by the Xilinx Spartan-3 FPGA at the working frequency of 100 MHz

关键词： Field programmable gate arrays Cameras Communication system control Detectors Centralized control Delay programmable logic arrays Scattering logic gates logic design

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A novel approach to testing LUT-based FPGAs

A novel approach to testing LUT-based FPGAs

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Shyue-Kung Lu Cheng-Wen Wu Department of Electronic Engineering Fu Jen Catholic University Taipei Taiwan Department of Electrical Engineering National Tsing Hua University Taiwan

A novel approach to testing look-up table (LUT) based field programmable gate arrays (FPGAs) is proposed in this paper. A general structure for the basic configurable logic array blocks (CLBs) is assumed. We group k CLBs in the column into a cell, where k denotes the number of inputs of a LUT. The whole chip is partitioned into disjoint one-dimensional arrays of cells. We assume that in each linear array, there is at most one faulty cell, and a faulty cell may contain multiple faulty CLBs. For the LUT, a fault may occur at the memory matrix, decoder, input or output lines. The stuck-on and stuck-off fault models are adopted for multiplexers. Our idea is to configure the cells to make each cell function bijective. In order to detect all faults defined, k+1 configurations are required. For each configuration, a minimal complete input sequence is applied to the leftmost cells of each linear array and the outputs of the rightmost cells can be observed. The input patterns can be easily generated with a k-bit counter and the resulting fault coverage is 100%.

关键词： Field programmable gate arrays Circuit faults Table lookup logic arrays programmable logic arrays Fault detection Manufacturing Circuit testing Counting circuits logic functions

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9A-2 Controlled 2D Cardiac Elasticity Imaging on an Isolated Perfused Rabbit Heart

9A-2 Controlled 2D Cardiac Elasticity Imaging on an Isolated...

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IEEE Symposium (IUS) Ultrasonics

作者： C. Jia R. Olafsson K. Kim R. S. Witte S.-W. Huang T. J. Kolias J. M. Rubin W. F. Weitzel C. Deng M. O'Donnell Department of Biomedical Engineering University of Washington Seattle WA USA Internal Medicine University of Washington Seattle WA USA Radiology University of Washington Seattle WA USA Department of Bioengineering and Mechanical Engineering University of Washington Seattle WA USA

Ultrasound strain and strain rate imaging have been proposed to detect myocardial muscle viability and contractility change. However, it's not easy to control experimental parameters and acquire high SNR data during in-vivo animal experiments. To address this, we performed 2D cardiac elasticity imaging on a well-controlled isolated retroperfused rabbit heart paced through the apex. The excitation-contraction decoupler, 2,3-butanedione monoxime (BDM) was used to optimize the maximum strain given frame acquisition rate, reducing the decorrelation due to excessive frame-to-frame strain. Under a local animal protocol, a heart was harvested from an anesthetized New Zealand White rabbit and prepared using a Langendorff preparation. Modified Oxygenated (95% 02 5% CO2) Krebs- Henseleit (K-H) buffer (PH 7.4, 37 degC) solution was retroperfused through the aorta. The heart was paced through the apex with electrodes at 3 Hz. The internal left ventricle (LV) pressure was recorded using a pressure meter connected to a water-filled latex balloon placed in the LV. The ECG signal was simultaneously recorded. Two linear array connected to a commercial US scanner (Sonix RP, Ultrasonix, Richmond, BC, Canada) were used to acquire RF data. The pacing signal, US RF, ECG and LV pressure data capturing were all synchronized using an field programmable gate array (FPGA) chip (ezFPGA-C6-6, Dallas logic, Piano, TX, USA). All these data were acquired before administering, during perfusion and after flushing BDM without/with the ligation of left anterior decending (LAD) artery At each data acquisition point, US RF data were acquired over two heart cycles (41 frames/cycle). 2D speckle tracking was applied to estimate displacement and strain. In this experiment, principal stretches were also derived using tracking results from two probes with resolution about 1.25 mm along its own axial direction. The principal stretches were compared for the normal heart and heart with ischemia or MI produced by

关键词： Elasticity Rabbits Heart Capacitive sensors Ultrasonic imaging Electrocardiography Radio frequency Animals Field programmable gate arrays programmable logic arrays

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An ANTLR-Based Approach to Compiling the Programing Language of Insect Intelligent Building

An ANTLR-Based Approach to Compiling the Programing Language...

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Chinese Automation Congress (CAC)

作者： Wenjie Chen Qiliang Yang Jianchun Xing Shuo Zhao Guangtong Xue Song Wang College of Defense Engineering Army Engineering University of PLA Nanjing China Guangzhou Design Station of Army Academ Guangdong China

I 2 B(Insect Intelligent Building) platform is a new type of building intelligent system. Lattice is a specialized programming language for I 2 B application development that we proposed earlier. Unfortunately, compiling Lattice codes into target codes running on the I 2 B hardware platform is still an unsolved problem. This paper proposes a compilation framework for Lattice. The entire compilation process is divided into multiple levels, and each level performs a specific translation work. We design key compiling algorithms for special language elements in Lattice, i.e., neighborhood interactive variables and higher-order operators. We conduct an experiment using a network summation case program in I 2 B. The experimental result shows our proposed compilation approach is effective.

关键词： Lattices Buildings C languages Syntactics Programming Domain specific languages programmable logic arrays

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