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检索条件"主题词=Programmable Logic Arrays"

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A 32b NMOS microprocessor with a large register file

A 32b NMOS microprocessor with a large register file

引用

IEEE International Conference on Solid-State Circuits (ISSCC)

作者： R. Sherburne M. Katevenis D. Patterson C. Sequin University of California Berkeley CA USA

This paper will discuss the characteristics of two scaled versions of a 32b reduced instruction set computer. A 4μm version (58mm 2 ) runs at 8MHz within 5% of expected speed, using 1.25W. The 3μm version, for which... 详细信息

关键词： MOS devices Microprocessors Registers Reduced instruction set computing Pipeline processing Decoding Delay Timing Circuits programmable logic arrays

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The Semi-Automatic Generation of Processing Element Control Paths for Highly Parallel Machines 84

The Semi-Automatic Generation of Processing Element Control ...

引用

Design Automation Conference

作者： T.M. Sabety D.E. Shaw B. Mathies Department of Computer Science Columbia University USA

ISBN: (纸本)9780818605420

This paper describes a recently implemented program that very rapidly generates control paths for different variants of the constituent processing elements of a particular massively parallel machine, the NON-VON Supercomputer. The program, called PLATO, accepts as input a set of instruction opcodes, together with associated control information, and produces as output a functionally correct, highly area-efficient set of PLA's for the processing elements. One novel aspect of the program is its use of a channel routing algorithm to generate a Weinberger Array layout for the OR-plane of the PLA. By supporting extremely rapid generation of processing elements with different instruction sets, PLATO facilitates "rapid turnaround" architectural experimentation of a sort that would otherwise be impractical. Use of the program has already yielded major area and performance improvements in the NON-VON processing element. Many of the techniques employed in the PLATO system should prove applicable to the semi-automatic layout of processing elements for other multiprocessor machines.

关键词： Process control Parallel machines Prototypes Area measurement Semiconductor device measurement Supercomputers programmable logic arrays MOS devices Very large scale integration Electric variables measurement

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Computer Aided Minimization Procedure for Boolean Functions 84

Computer Aided Minimization Procedure for Boolean Functions

引用

Design Automation Conference

作者： N.N. Biswas Indian Institute of Science Bangalore India

ISBN: (纸本)9780818605420

The paper describes CAMP, a Computer Aided Minimization Procedure for Boolean functions. The procedure is based on theorems of switching theory and fully exploits the power of degree of adjacency. The program does not generate any superfluous prime implicant and all the essential and selective prime implicants are chosen with no or minimum iteration. For shallow functions consisting mainly of essential prime implicants (EPIs) and a few selective prime implicants (SPIs), CAMP produces the exact minimal sum of product form. For dense functions consisting of a large number of inter-connected cyclic SPI chains, the solution may not be exactly minimal, but near minimal.

关键词： Boolean functions Minimization methods programmable logic arrays Very large scale integration logic design logic circuits Large scale integration Economic indicators Writing

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Porting of a CMOS VLSI Chip from 2.5 Micron to 1.75 Micron Design Rules

Porting of a CMOS VLSI Chip from 2.5 Micron to 1.75 Micron D...

引用

European Conference on Solid-State Circuits (ESSCIRC)

作者： P.W. Diodato A.K. Goksel F.D. La Rocca W.W. Troutman AT and T Bell Laboratories Inc. Murray Hill NJ USA

The porting, or updating of a 2.5 micron CMOS VLSI design into 1.75 micron design rules has been completed. This porting involves three major undertakings: (1) reduction of all feature sizes in accordance to the new design rules, (2) simulation at the transistor level of the 1.75 micron circuit behavior and (3) incorporation of several new architectural features in the original topology. Despite the extent of logic changes the resulting design was completed in an extremely short period of time. This paper describes a process by which this and other VLSI designs which require state of the art performance can be transformed into a new generation of design rules in a prompt and efficient manner.

关键词： Very large scale integration programmable logic arrays logic design Circuit topology Circuit simulation CMOS logic circuits logic arrays Frequency diversity Hardware Adders

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An integrated modular and standard cell IC design method

An integrated modular and standard cell IC design method

引用

IEEE International Conference on Solid-State Circuits (ISSCC)

作者： R. Kasai K. Fukami K. Tansho H. Kitazawa S. Horiguchi NTT Atsugi and Musashino Elec. Comm. Labs. Kanagawa and Tokyo Japan

An integrated method which combines modular and standard -cell techniques with automated PLA design to implement a 16b microcomputer will be reported. A CAD system was used to achieve less than 20 man-month design time.

关键词： Design methodology Very large scale integration programmable logic arrays Circuits Wiring Microcomputers Design automation CMOS process CMOS technology MOSFETs

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A comparison of mixed gate array and custom IC design methods

A comparison of mixed gate array and custom IC design method...

引用

IEEE International Conference on Solid-State Circuits (ISSCC)

作者： C. Erdelyi R. Bechade M. Concannon W. Hoffman IBM General Tech. Div. Essex Junction VT USA

This paper will present a comparison of gate-array, mixed gate-array-custom and full custom implementations of a 32b NMOS microprocessor. Use of 5V and 3.4V on-chip supply voltages and automated gate-array design for parts of the chip has resulted in a speed and power dissipation of 230ns/2.8W, comparable to the full-custom approach (170ns/3W) in half the design time.

关键词： Design methodology Capacitance Wiring Voltage Delay logic design logic circuits Driver circuits programmable logic arrays Circuit testing

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Delay and Power Optimization in VLSI Circuits 84

Delay and Power Optimization in VLSI Circuits

引用

Design Automation Conference

作者： L.A. Glasser L.P.J. Hoyte Electrical Engineering and Computer Science Department Research Laboratory of Electronics Massachusetts Institute of Technology Cambridge MA USA Prime Computer Inc. Framingham MA USA

The problem of optimally sizing the transistors in a digital MOS VLSI circuit is examined. Macro-models are developed and new theorems on the optimal sizing of the transistors in a critical path are presented. The res... 详细信息

ISBN: (纸本)9780818605420

关键词： Delay Very large scale integration Circuit optimization Large scale integration programmable logic arrays MOS devices Macrocell networks Silicon Laboratories Power engineering computing

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Cell Compilation with Constraints 84

Cell Compilation with Constraints

引用

Design Automation Conference

作者： C. Lursinsap D. Gajski Department of Computer Science University of Illinois Urbana-Champaign Urbana IL USA

ISBN: (纸本)9780818605420

This paper describes a cell compiler that translates cell descriptions given in form of Boolean equations including pass transistors into layout descriptions in Caltech Intermediate Form (CIF). The translation process is constrained by given height and width of the cell and the position of each I/O signal on the boundary of the cell. Furthermore, the size of each transistor as well as power consumption can be arbitrarily chosen. This cell compiler allows routing through the cell in any direction. The cell architecture is based on PLA structures.

关键词： Routing Libraries Energy consumption Algorithm design and analysis Digital systems Computer science programmable logic arrays Delay effects Silicon logic circuits

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A VLSI FSM Design System 84

A VLSI FSM Design System

引用

Design Automation Conference

作者： M.J. Meyer P. Agrawal R.G. Pfister AT and T Bell Laboratories Holmdel USA AT and T Bell Laboratories Murray Hill NJ USA AT&T Bell Labaratories Murray Hill NJ USA

ISBN: (纸本)9780818605420

This paper describes a fully automated finite-state machine (FSM) synthesis system. The FSM is realized as a PLA. This synthesizer accepts a high-level description of the FSM and generates a mask level layout. Several simulation models are produced at different levels of abstraction; these models can be integrated with other modules on the chip to aid in the debugging of the overall VLSI chip design. Valuable information on speed, area, and testability of the PLA can be obtained through a collection of audit programs. This system has been used to design complex controllers for many VLSI chips at AT&T Bell Laboratories. Although a PLA implementation is assumed, the system can be extended to synthesize a random logic implementation of the FSM.

关键词： Very large scale integration programmable logic arrays Design methodology Circuits Automatic control Automatic generation control Clocks Synthesizers Debugging Chip scale packaging

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Functional Design Verification by Multi-Level Simulation 84

Functional Design Verification by Multi-Level Simulation

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Design Automation Conference

作者： K. Tham R. Willoner D. Wimp Intel Corporation Santa Clara CA USA Intel Corporation Hillsboro OR USA

ISBN: (纸本)9780818605420

This paper introduces Intel's functional CAD design environment and methodology. The generation of an accurate behavioral model for use in systems design validation and for comparisons with lower-level components is described. The need for both an RTL and a schematics simulator in Intel's hierarchical design methodology is explained. Finally, the paper shows how these two simulators have been linked together in two ways for two different purposes: for RTL-schematics verification, and for very large logic simulation runs.

关键词： Integrated circuit modeling logic design Design automation Hardware design languages Microarchitecture Testing Design methodology Refining programmable logic arrays Switching circuits

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