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检索条件"主题词=Programmable Logic Arrays"

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Technology mapping for minimizing gate and routing area 98

Technology mapping for minimizing gate and routing area

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Design, Automation and Test in Europe Conference and Exhibition

作者： A. Lu G. Stenz F.M. Johannes Institute of Electronic Design Automation Technical University Munich Munich Germany

ISBN: (纸本)9780818683596

This paper presents a technology mapping approach for the standard cell technology, which takes into account both gate area and routing area so as to minimize the total chip area after layout. The routing area is estimated using two parameters available at the mapping stage; one is the fanout count of a gate, and the other is the "overlap of fanin level intervals". To estimate the routing area in terms of accurate fanout counts, an algorithm is proposed which solves the problem of dynamic fanout changes in the mapping process. This also enables us to calculate the gate area more accurately. Experimental results show that this approach provides an average reduction of 15% in the final chip area after placement and routing.

关键词： Routing Integrated circuit interconnections Process design Hip Delay Electronic design automation and methodology programmable logic arrays Digital systems Very large scale integration Fabrication

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A dual processor serial data controller chip

A dual processor serial data controller chip

引用

IEEE International Conference on Solid-State Circuits (ISSCC)

作者： G. Louie J. Wipfli A. Ebright Intel Corp. Santa Clara CA USA

A DUAL PROCESSOR microprogrammable chip that implements a specialized architecture for high-speed serial data controllers will be described. The chip measures 218 mils by 244 mils and contains 22,000 transistors which yields a device density of 0.41 devices per square mil. This device count represents a four-fold increase in chip complexity over an earlier model". The processing capability supported by this chip relieves the system CPU of many of the low-level control tasks associated with controller applications. Operations are specified by the systems CPU and executed independently by the chip. Once an operation has been specified, no system CPU intervention is required

关键词： Process control Registers Control systems programmable logic arrays System buses Microprocessors Hardware Read only memory Density measurement Semiconductor device measurement

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A design for concurrent error detections in FPLAs

A design for concurrent error detections in FPLAs

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Great Lakes Symposium on VLSI

作者： Tsin-Yuan Chang Jean-Bean Hsu Cheng-Chi Wang Yu-Shen Lin Department of Electrical Engineering National Tsing Hua University Hsinchu Taiwan

ISBN: (纸本)0818626100

A combined design of four concurrent error detection (CED) schemes-the alternating logic scheme, duplication of the on-set scheme, duplication of the off-set scheme, and the parity checking scheme, is proposed for field programmable logic arrays (FPLAs) which inherently has unutilized elements. One of the four CED schemes can be implemented by the proposed circuit and the unutilized elements with the constraint that the unused elements can be programmed as parts of test logic.< >

关键词： programmable logic arrays logic design Circuit testing logic testing Pins logic circuits Circuit synthesis Electrical fault detection Fault detection Circuit faults

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Design of 3D printed lens antenna for 5G applications

Design of 3D printed lens antenna for 5G applications

引用

IEEE MTT-S International Microwave and RF Conference

作者： Goutha Reddy Shalini D.Rama Krishna Gs Karthikeya Shiban K. Koul CEME University College of Engineering Osmania University Hyderabad India Centre for Applied Research in Electronics IIT Delhi New Delhi India

ISBN: (纸本)9781665458764

This paper demonstrates a high gain 3D printed lens antenna at 28GHz for 5G applications. The lens is a hemispherical lens designed to improve the gain of a microstrip patch antenna. The design technique employed here is to chop the edges of the lens to realize a compact antenna. The proposed antenna is observed to provide a gain of 11.70 dBi at 28GHz.

关键词： Radio frequency Three-dimensional displays 5G mobile communication Patch antennas programmable logic arrays Three-dimensional printing Microwave theory and techniques

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Memmap: technology mapping algorithm for area reduction in FPGAs with embedded memory arrays using reconvergence analysis

Memmap: technology mapping algorithm for area reduction in F...

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Design, Automation and Test in Europe Conference and Exhibition

作者： A. Manoj Kumar J. Bobba V. Kamakoti Indian Institute of Technology Madras Indian Institute of Technology Madras India

Modern day field programmable gate arrays (FPGA) include in addition to look-up tables, reasonably big configurable embedded memory blocks (EMB) to cater to the on-chip memory requirements of systems/applications mapped on them. While mapping applications on to such FPGAs, some of the EMBs may be left unused. This paper presents a methodology to utilize such unused EMBs as large look-up tables to map multi-output combinational sub-circuits of the application, which, otherwise would be mapped on to a number of small look-up tables (LUT) available on the FPGA. This in turn leads to a huge reduction in the area of the FPGA, utilized for mapping an application. Experimental results show that our proposed methodology, when employed on popular benchmark circuits, can lead to additional 50% reduction in area utilized when compared with other methodologies reported in the literature.

关键词： Field programmable gate arrays Algorithm design and analysis Random access memory Table lookup programmable logic arrays System-on-a-chip Circuit synthesis Read-write memory Lattices logic devices

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Cradle-to-Gate Environmental Impact Assessment of a Polylactic Acid Polymer-Based Adjustable Air Stone for Adjustable Microbubbles Generation

Cradle-to-Gate Environmental Impact Assessment of a Polylact...

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International Conference on Humanoid, Nanotechnology, Information Technology, Communication and Control, Environment and Management (HNICEM)

作者： Danielle Joseph Buban R-Jay Relano Ronnie Concepcion Alvin Culaba Department of Mechanical Engineering De La Salle University Manila Philippines College of Engineering Manuel S. Enverga University Foundation Lucena Philippines Department of Manufacturing Engineering and Management De La Salle University Manila Philippines Intelligent Systems Research Unit Center for Engineering and Sustainability Development Research De La Salle University Manila Philippines Plant and Soil Health Research Unit Center for Natural Sciences and Environmental Research De La Salle University Manila Philippines

ISBN: (数字)9798350381177

ISBN: (纸本)9798350381184

Aeration is important in the application of aquaponics and hydroponics to sustain adequate oxygen levels in water systems to support the biological processes of fish, plants, and other organisms. The study concentrated on the production to retail life cycle assessment of a 3D-printed, adjustable aquarium air stone made of a polylactic acid (PLA) polymer filament. Input-process-output was employed to describe the structure and behavior of a system or process. It was used in conjunction with the life cycle assessment (LCA) software, openLCA. ReCiPe (H) 2016 was the impact assessment technique employed in this investigation as the life cycle analysis approach to quantify a specific set of parameters that represent the environmental effects of emissions and resource extractions and turns them into numerical data. From the simulated calculations of the Life Cycle Inventory Assessment, it was determined that terrestrial ecotoxicity, global warming, and fossil resource scarcity are the top three contributors in the air stone's environmental impact having the highest numerical value in the different impact categories with values amounting to 14.75476 kg 1,4-DCB, 8.38423 kg CO2 eq, and 1.89515 kg oil eq respectively. Implying that the product has a high potential to impair the health and diversity of terrestrial organisms, the global climate system's balance, and the availability and of fossil energy supplies. It implies that the environmental impact of 3D printing PLA-based air stones is assessed mostly during the process of production, rather than during use or end-of-life.

关键词： Life cycle assessment Three-dimensional displays Oils Transportation programmable logic arrays Production Three-dimensional printing

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Behavioural Specification Of Programs For Modular Reconfigurable logic Controllers

Behavioural Specification Of Programs For Modular Reconfigur...

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International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES)

作者： M. Adamski Institute of Computer Engineering and Electronics University Of Zielona Góra Poland

In the paper the outline of the modular, reconfigurable logic controller design is presented. As the initial specification, sequential function chart (SFC-1131) is considered, as well as its equivalent textual specification in structured text. The focused items of design are: modification of the initial specification of the controller by means of introducing separate control part, described as SFC without complex conditions of transitions and only with combinational qualifiers and outputs, and a data path on register transfer level. In the proposed design methodology, after "lifting" such kind of sound SFC is treated as a particular kind of modular control interpreted Petri net. It is first formally analysed, and later described and simulated in HDL environment. Such verified and tested behavioural specification is mapped directly into FPGA matrix structure of reconfigurable logic controller by using standard or dedicated synthesis tools. The dedicated data path is treated as a complex functional building block, which is combined from previously designed modules - IP cores

关键词： Reconfigurable logic Control systems Hardware design languages Switches Embedded system logic design Design methodology Belts Field programmable gate arrays programmable logic arrays

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Combining spatial and topological data in a spatiotemporal relational model

Combining spatial and topological data in a spatiotemporal r...

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IEEE International Conference on Intelligent Engineering Systems (INES)

作者： A.B. Novak Z. Tuza Faculty of Information Technology Pázmány Péter Catholic University Budapest Hungary Bánki Donát Faculty of Mechanical Engineering Budapest Tech Budapest Hungary Computer and Automation Institute and Department of Computer Sci University of Veszprém Budapest Hungary

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Electromagnetic Analysis and Performance Comparison of Fully 3D-printed Antennas

Electromagnetic Analysis and Performance Comparison of Fully...

引用

Progress in Electromagnetic Research Symposium (PIERS)

作者： R. Colella F. Chietera L. Catarinucci A. Casula G. Montisci G. Gatto A. Michel P. Nepa H. Rogier University of Salento Lecce Italy University of Cagliari Cagliari Italy University of Pisa Pisa Italy Internet Technology and Data Science Lab Ghent University Gent Belgium

ISBN: (数字)9781728134031

ISBN: (纸本)9781728134048

In this work, the possibility of directly prototyping antennas by exploiting additive manufacturing 3D-printing technology is investigated. In particular, the availability of printable filaments with interesting conductive properties allows for printing of even the antenna conductive elements. Three samples of a 2.45 GHz microstrip patch antenna have been 3D-printed by using different approaches and materials, and their performance evaluated and compared. In particular, the same dielectric substrate printed in polylactic acid (PLA) has been adopted in all cases, whilst copper tape and two different conductive filaments have been used to realize the conductive parts of the three antenna samples, respectively. Even if an expected radiation efficiency reduction has been observed for the conductive filament case, the comparative analysis clearly demonstrates that 3D-printing technology can be exploited to design working fully-printed antennas, including the conductive parts.

关键词： Substrates programmable logic arrays Conductivity Springs Printing Patch antennas

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Binary and multi-valued SPFD-based wire removal in PLA networks

Binary and multi-valued SPFD-based wire removal in PLA netwo...

引用

IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： S. Sinha S.P. Khatri R.K. Brayton A.L. Sangiovanni-Vincentelli Dept. of Electr. Eng. & Comput. Sci. California Univ. Berkeley CA USA VLSl CAD Research Group Department of ECE University of Colorado Boulder CO USA Department of EECS CAD Research Group University of California Berkeley CA USA

This paper describes the application of binary and multivalued SPFD-based wire removal techniques for circuit implementations utilizing networks of PLAs. It has been shown that a design style based on a multi-level network of approximately equal-sized PLAs results in a dense, fast, and crosstalk-resistant layout. Wire removal is a technique where the total number of wires between individual circuit nodes is reduced, either by removing wires, or replacing them with other existing wires. Three separate wire removal experiments are performed. Either wire removal is invoked before clustering the original netlist into a network of PLAs, or after clustering, or both before and after clustering. For wire removal before clustering, binary SPFD-based wire removal is used. For wire removal after clustering, multi-valued SPFD-based wire removal is used since the multi-output PLAs can be viewed as multi-valued single output nodes. We demonstrate that these techniques are effective. The most effective approach is to perform wire removal both before and after clustering. Using these techniques, we obtain a reduction in placed and routed circuit area of about 11%. This reduction is significantly higher (about 20%) for the larger circuits we used in our experiments.

关键词： Wire Intelligent networks programmable logic arrays Design automation Crosstalk logic circuits Routing Field programmable gate arrays

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