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检索条件"主题词=Programmable Logic Arrays"

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Efficient decomposition of assigned sequential machines and Boolean functions for PLD implementations

Efficient decomposition of assigned sequential machines and ...

引用

Electronic Technology Directions to the Year 2000

作者： L. Jozwiak F. Wolf Electrical Engineering Eindhovan University of Technology Eindhoven Netherlands Technische Universiteit Eindhoven Eindhoven Noord-Brabant NL Fac. of Electr. Eng. Eindhoven Univ. of Technol. Netherlands

programmable devices impose hard constraints on the size of circuits that can be implemented with them or with their blocks. Therefore, decompositional implementation of large functions is not a choice but a real necessity in this case. The objective of the new decomposition method presented is to implement a complex Boolean function or an assigned sequential machine with a minimal number of constrained building blocks and minimal connections between the blocks. The method aims at solving problems with hard constraints in multiple dimensions. It differs substantially from the methods for solving similar simpler one dimensional problems. The method is very general and, after some small changes, it can be applied to many other partitioning problems. The experimental results show that the method is very efficient.< >

关键词： Boolean functions logic devices programmable logic devices Combinational circuits programmable logic arrays Field programmable gate arrays Input variables Output feedback Circuit synthesis HDTV

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Wearable wireless accelerometer with embedded fall-detection logic for multi-sensor ambient assisted living applications

Wearable wireless accelerometer with embedded fall-detection...

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IEEE SENSORS

作者： Andrea Lombardi Massimo Ferri Gabriele Rescio Marco Grassi Piero Malcovati Department of Electrical Engineering University of Pavia Italy

In this paper we present a wearable wireless accelerometer device for people fall detection in ambient assisted living (AAL) applications, communicating with care holders and relatives of the assisted person through an ADSL based gateway. The wearable system is a PCB with a commercial three-axes, digital-output MEMS accelerometer chip, a ZigBee transceiver and a programmable logic (FPGA). The raw acceleration stream from the MEMS sensor is processed by suitable algorithms on the FPGA, whose aim is to detect potential falls and their level of confidence, delivering an alarm information to the gateway by means of the ZigBee transceiver. Several sessions of data collection with real actors have been performed to define and characterize fall detection algorithms. Experimental results show that the accelerometer is a fundamental component of a multi-sensor network system and on this basis a custom device has been realized.

关键词： Accelerometers logic devices Micromechanical devices ZigBee Transceivers Field programmable gate arrays programmable logic arrays programmable logic devices Acceleration Sensor phenomena and characterization

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Cascade Two-dimensional Locality Preserving Projections for Face Recognition

Cascade Two-dimensional Locality Preserving Projections for ...

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Pacific-Asia Conference on Circuits, Communications and Systems, PACCS

作者： Xiaoguo Wang Ming Tian Cong Wang Yong Huang Jun Liu Xiongwei Zhang Institute of Communications Engineering People''s Liberation Army University of Science and Technology Nanjing China

In this paper, we propose a novel algorithm for face feature extraction, namely the cascade two-dimensional locality preserving projections (C2DLPP), which directly extracts the proper features from image matrices based on locality preserving criterion. Experiments on ORL and PIE face database are performed to test and evaluate the proposed algorithm. The results demonstrate the effectiveness of proposed algorithm.

关键词： Face recognition Feature extraction Principal component analysis Image databases Circuits programmable logic arrays Spatial databases Performance evaluation Testing Pattern recognition

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Audio and Video Transmission Card Based on PCI9054 Bus Controller

Audio and Video Transmission Card Based on PCI9054 Bus Contr...

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International Workshop on Education Technology and Computer Science, ETCS

作者： Zirui Huang Xien Ye Institute of Circuits and Systems University Ningbo Ningbo Zhejiang China

ISBN: (纸本)9781424463886;9780769539874

The performance of PCI9054 bus controller is introduced in this paper, high-speed Audio and Video transmission card based on PCI9054 bus controller is designed with programmable logic gate array, we could realize data processing and high-speed transmission between PC and Audio and Video transmission card. Hardware and software programs of this transmission card are also introduced and the feasibility of the transmission card is verified through experiments.

关键词： Field programmable gate arrays Control systems logic design Read-write memory programmable logic arrays Integrated circuit interconnections Circuits and systems Data processing Computer science education Educational technology

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Spatial Clustering with Obstacles Constraints Using PSO-DV and K-Medoids

Spatial Clustering with Obstacles Constraints Using PSO-DV a...

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2008 3rd International Conference on Intelligent System and Knowledge Engineering(第三届智能系统与知识工程国际会议)(ISKE 2008)

作者： Xueping Zhang Gaofeng Deng Wei Ding Jiayao Wang Zhongshan Fan Information Science& Engineering Henan Univ.of Technology Zhengzhou Henan China 450001 Key Laborator Information Science& Engineering Henan Univ.of Technology Zhengzhou Henan China 450001 Information Science& Engineering Henan Univ.of Technology Zhengzhou Henan China 450001 Surveying & M Henan Academy of Traffic Science & Technology Zhengzhou Henan China 450052

Spatial Clustering with Obstacles Constraints(SCOC)has been a new topic in Spatial Data Mining(SDM).Inthis paper,we propose an advanced Particle SwarmOptimization(PSO)and Differential Evolution(DE)methodfor *** the process of doing so,we first developed anovel spatial obstructed distance using PSO-DV(Particle SwarmOptimization with Differentially perturbed Velocity)based ongrid model to obtain obstructed distance,which is namedPDGSOD,and then we presented a new PDKSCOC based onPSO-DV and K-Medoids to cluster spatial data with *** experimental results show that PDGSOD iseffective,and PDKSCOC can not only give attention to higherlocal constringency speed and stronger global optimum search,but also get down to the obstacles constraints and practicalitiesof spatial clustering;and it performs better than Improved K-Medoids SCOC(IKSCOC)in terms of quantization error andhas higher constringency speed than Genetic K-Medoids SCOC(GKSCOC).

关键词： Clustering algorithms Particle swarm optimization Knowledge engineering Data mining Quantization Genetics Intelligent systems Laboratories programmable logic arrays Electronic mail

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COPACOBANA A Cost-Optimized Special-Purpose Hardware for Code-Breaking

COPACOBANA A Cost-Optimized Special-Purpose Hardware for Cod...

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Annual IEEE Symposium on Field-programmable Custom Computing Machines (FCCM)

作者： Sandeep Kumar Christof Paar Jan Pelzl Gerd Pfeiffer Manfred Schimmler Horst Gortz Institute for IT Security Ruhr University of Bochum Germany Department of Computer Science Faculty of Engineering Christian Albrecht University Germany

Cryptanalysis of symmetric and asymmetric ciphers is computationally extremely demanding. Since the security parameters of almost all practical crypto algorithms are chosen such that attacks with conventional computers are computationally infeasible, the only promising way to tackle existing ciphers (assuming no mathematical breakthrough) is to build special-purpose hardware. This contribution presents a special-purpose hardware labeled COPACOBANA (cost-optimized parallel code breaker), which is optimized for running crypt-analytical algorithms with low communication overhead. The price-performance ratio as primary and a cost margin of less than US$ 10,000 as secondary design goal led to a reconfigurable computer built as cluster of programmable logic devices

关键词： Hardware Field programmable gate arrays Computer architecture Cryptography Costs Computer security programmable logic arrays Backplanes Computer science Clustering algorithms

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A Support System for Home Care Service Based on Multi-agent System

A Support System for Home Care Service Based on Multi-agent ...

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International Conference on Information, Communications and Signal Processing

作者： G. Itabashi M. Chiba K. Takahashi Y. Kato Scientific Corporation Sendai Japan Sendai National College of Technology Sendai Japan

According to the increase of high quality welfare services in Japan, welfare services need engineering supports. In this paper, we develop a support system for a home care service, using a multi-agent system. The decision of a care schedule is performed autonomously by the negotiations among agents so that it is sufficient for clients and helpers to confirm schedules settled by the agents. They can confirm the schedules using PDAs, which can be easily handled even by elders. Consequently, it is expected that our support system reduces the total cost of a home care service

关键词： Multiagent systems Scheduling Personal digital assistants Medical services Qualifications Costs Ontologies Educational institutions programmable logic arrays Insurance

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On input permutation technique for multiple-valued logic synthesis

On input permutation technique for multiple-valued logic syn...

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International Symposium on Multiple-Valued logic

作者： Y. Hata N. Kamiura K. Yamato Department of Computer Engineering Himeji Institute of Technology Himeji Japan

An input permutation technique with respect to multiple valued logic synthesis is introduced. First, it is applied to multiple valued sum of products expressions where sum refers to TSUM. Some upper bounds are clarified on the number of implicants in minimal sum of products expressions for one variable and two variable functions with permuted logic values. An experiment was done on randomly generated functions. The result shows that we can have a saving of approximately 15% on the average by permuting input values. Next, we compare the input permutation with output permutation. As a result, input permutation and output permutation yield a similar saving rate of implicants and output permutation has an advantage of hardware cost and minimization times. Moreover, we show that the use of input permutation for multiple valued sum of products expressions with window literals yields similar results when one uses sum of products expressions with set literals.

关键词： Hardware Costs Minimization programmable logic arrays logic design Input variables Upper bound Design optimization Decoding Circuits

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PLATYPUS: A PLA Test Pattern Generation Tool

PLATYPUS: A PLA Test Pattern Generation Tool

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Design Automation Conference

作者： Ruey-Sing Wei A. Sangiovanni-Vincentelli Department of EECS University of California Berkeley CA USA

PLATypus (PLA Test pattern generation and logic simulation tool) is an efficient tool for large PLAs which is interfaced constrained/unconstrained, simple/multiple folding program PLEASURE and the logic minimizer ESPRESSO II-C developed at the University of California at Berkeley. PLATYPUS uses biased random test generation as a quick preprocess followed by a deterministic test generation process to achieve the best balance between efficient run time and test set minimality. The algorithm adopted in the deterministic phase is exact, i.e., it achieves the highest possible test coverage by generating a test for every testable fault. Powerful heuristics are introduced in the area of fault processing order, backend fault simulation, "don't-care" bit fixing, and on-the-fly test compaction to achieve the best performance of PLATYPUS. The deterministic test generation algorithm is based on both complementation and tautology check of a logic cover. Both complementation and tautology check are performed by an advanced method used in the logic minimizer ESPRESSO-II. PLATYPUS supports both folded and unfolded PLAs, and both crosspoint and stuck-at fault models. PLATYPUS can also be used as a logic simulation tool and redundancy identifier. Test pattern generation has been performed by PLATYPUS on a large number of industrial PLAs.

关键词： programmable logic arrays Test pattern generators logic testing Very large scale integration Compaction Redundancy Performance evaluation logic design Feedback System testing

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RTD-based compact programmable gates

RTD-based compact programmable gates

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International Joint Conference on Neural Networks (IJCNN)

作者： J.M. Quintana M.J. Avedillo H. Pettenghi Instituto de Microelectrónica de Sevilla Centra Nacional de Microelectrónica Seville Spain

This work presents novel and extremely compact implementations of programmable gates on the basis of the multi-threshold threshold gate concept. The circuit consists of resonant tunnelling diodes (RTDs) and heterostructure field effect transistors (HFETs) and its operating principle is based on the controlled quenching of clocked series-connected RTDs. The proposed generic circuit topology is presented and the methodology to design specific programmable gates is introduced. A number of programmable gates are shown and their operation is validated.

关键词： Resonant tunneling devices logic functions programmable logic arrays logic devices Diodes logic design Switches Electronic mail RLC circuits Design methodology

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