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检索条件"主题词=Programmable Logic Arrays"

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A methodology for the test of embedded compiled cells

A methodology for the test of embedded compiled cells

引用

Custom Integrated Circuits Conference (CICC)

作者： M.A. Samad T. Butzerin VLSI Technology Inc. San Jose CA USA

The use of compilers for structured cells such as RAMs, ROMs, multipliers and PLAs (programmable logic arrays) has become widespread in the design of application-specific integrated circuits (ASICs). The authors present a methodology for testing circuits made from these compiled cells. The key elements of this methodology are the vector compilers that generate test suites for the compiled cells and an isolation strategy that allows these test suites to be applied to embedded functional blocks.< >

关键词： Circuit testing Read only memory programmable logic arrays Application specific integrated circuits Circuit faults Very large scale integration Integrated circuit technology Timing Shape Program processors

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A transistor level placement tool for custom cell generation

A transistor level placement tool for custom cell generation

引用

International Conference on VLSI Design

作者： R.K. Dash T. Pramod V. Vasudevan M. Ramakrishna Department of Electrical Engineering Indian Institute of Technology Madras India

In this paper, we present a transistor level placer suitable for the macro cell design style. The Eulerian path finding algorithm is used to create locally optimal placements of groups of transistors, called stacks. Typically however there are large disparities in the sizes of the various stacks obtained. It is therefore not always possible to meet the desired cell aspect ratio/height/width specifications. In our placer, these stacks can be reshaped so that the constraints on the cell are met. The optimisation tool used is simulated annealing. Placements for cells containing several hundred transistors were generated using this method.

关键词： Libraries Circuit simulation Simulated annealing Transistors Parasitic capacitance Very large scale integration CMOS technology Costs programmable logic arrays CMOS logic circuits

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A notation for describing multiple views of VLSI circuits

A notation for describing multiple views of VLSI circuits

引用

Design Automation Conference

作者： J.-L. Baer M.-C. Liem L. McMurchie R. Nottrott L. Snyder W. Winder NW Laboratory for Integrated Systems Department of Computer Science University of Washington Seattle WA USA

A declaration hierarchical notation is introduced that allows the parametric representation of entire families of VLSI circuits. Layout, schematic diagrams and network structure are all accommodated by the notation in a way that emphasizes common elements. The notation is the basic of a structured environment for developing design generators as well as capturing design expertise.< >

关键词： Very large scale integration Circuit synthesis Circuit simulation Design automation programmable logic arrays Laboratories Computer science Application specific integrated circuits Contracts Databases

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Practical built-in test of CMOS state machines with realistic faults

Practical built-in test of CMOS state machines with realisti...

引用

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： M. Katoozi M. Soma Seattle Silicon Corporation Bellevue WA USA Department of Electrical Engineering University of Washington Seattle WA USA

A design-for-test scheme is presented that is capable of testing programmable and register logic arrays with the same low-cost test hardware. This scheme detects real faults resulting from mask defects in the circuit, is practical to implement, and can be adopted as a built-in-test system using readily available modules in application-specific integrated circuits.< >

关键词： Built-in self-test logic testing Circuit testing programmable logic arrays Design for testability Registers CMOS logic circuits logic design Hardware Electrical fault detection

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Power Testing of an FPGA based System Using Modelsim Code Coverage capability

Power Testing of an FPGA based System Using Modelsim Code Co...

引用

IEEE Design and Diagnostics of Electronic Circuits and Systems (DDECS)

作者： Khalil Arshak Essa Jafer Christian Ibala Department of Electronic and Computer Engineering University of Limerick Limerick Ireland CAE Logic Drive Xilinx Inc. Dublin Ireland

Field programmable gate arrays (FPGAs) play many important roles, ranging from small glue logic replacement to System-on-Chip designs. Nevertheless, FPGA vendors can not accurately specify the energy consumption information of their products on the device data sheets because the energy consumption of FPGAs is strongly dependent on target circuit including resource utilization, logic partitioning, mapping, placement and route. While major CAD tools have started to report average power consumption under given transition activities, energy optimal FPGA design demands more detailed energy estimation. The target design is telemetry system used for health monitoring applications. The FPGA is acting as the controller unit of both transmitter and receiver. Transmitter side is reading data from interfaced sensors. Verilog-HDL has been used to implement the required functions of the FPGA. In this paper, the power performance of the FPGA based design will be investigated using XILINX Xpower tool. Modelsim Code coverage feature has been incorporated to make sure that the test-bench cover all the nets branch statement of the design and create the most accurate Value Change Dump (VCD) file for the power consumption estimation.

关键词： System testing Field programmable gate arrays Power system modeling Energy consumption programmable logic arrays logic devices Transmitters logic design System-on-a-chip Circuits

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The Implementation of a State Machine Compiler

The Implementation of a State Machine Compiler

引用

Design Automation Conference

作者： C. Kingsley Centre de Recherche EuropeenLes Taissounieres VLSI Technology Inc. La Valbonne France

This paper describes VTIstate, VLSI Technology's state machine compiler. The compiler derives combinational logic and registers to make a state machine, and synthesizes the combinational logic with three optimization steps. The 1986 Design Automation conference synthesis benchmark set is used to compare the results with previously reported logic synthesis programs.

关键词： Network synthesis programmable logic arrays Design automation Permission Very large scale integration logic design Automatic control Lighting control Design optimization Cost function

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A balanced multilevel decomposition method 95

A balanced multilevel decomposition method

引用

European Design and Test (ED&TC) Conference

作者： H. Selvaraj T. Luba Institute of Telecommunications Warsaw University of Technology Warsaw Poland

ISBN: (纸本)9780818670398

A general decomposition concept is presented in this paper. The main strategy behind the presented Multilevel Decomposition Method (MDM) is striking a balance between serial decomposition and parallel decomposition. Such a strategy, on one hand, is capable of detecting and utilizing the fact that a group of outputs may depend on the same set of input variables and on the other hand eliminates the redundant variables of different outputs. The method is applicable to a variety of field programmable gate arrays. The results prove that the method is efficient and does not suffer from its generality.< >

关键词： Field programmable gate arrays programmable logic arrays Boolean functions logic devices Process design Input variables Operating systems Workstations Minimization Process control

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A reconfigurable architecture for emulating large-scale bio-inspired systems

A reconfigurable architecture for emulating large-scale bio-...

引用

Congress on Evolutionary Computation

作者： J. Manuel Moreno Jordi Madrenas Electronic Engineering Department Technical University Catalunya Barcelona Spain

In this paper we shall present a reconfigurable architecture that has been specifically conceived for emulating large-scale bio-inspired systems. The architecture is organized as a regular array of programmable elements that can be used either as fine grain logic elements or configured in order to construct massively parallel SIMD (single instruction multiple data) machines. As it will be explained, the specific features that have been included in the architecture permit the efficient implementation of a wide range of complex systems.

关键词： Reconfigurable architectures Large-scale systems Computer architecture Hardware Computer aided manufacturing CADCAM Neural networks programmable logic arrays Macrocell networks Protocols

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Pulsed laser ablation of epitaxial and conductive LaNiO/sub 3/ thin films for ferroelectric device applications

Pulsed laser ablation of epitaxial and conductive LaNiO/sub ...

引用

International Symposium on Electrets (ISI)

作者： Tao Yu Yanfeng Chen Li Sun Sibei Xiong Hailong Zhou Xiaoyuan Chen Zhiguo Liu Naiben Ming Lianjie Shi National Laboratory of Solid State Microstructures Nanjing University Nanjing China Department of Materials Science and Engineering Nanjing University of Science and Technology of PLA Nanjing China

ISBN: (纸本)0780326954

Epitaxial LaNiO/sub 3/ (LNO) thin films have been fabricated on [001]SrTiO/sub 3/ (STO) and [001]LaAlO/sub 3/ (LAO) single crystal substrates at 30 Pa oxygen partial pressure and 700/spl deg/C substrate temperature by pulsed laser ablation (PLA) using pulsed excimer laser. X-ray /spl theta/-2/spl theta/ scan, X-ray /spl phi/ scan were used to characterize the as-deposited LNO thin films. The resistance versus temperature of LNO/STO and LNO/LAO were performed by standard DC four point probe method. Down to 80 K the epitaxial LNO thin films showed good metallic behavior. The resistivity of epitaxial LNO thin film was 2.25/spl times/10/sup -6/ /spl Omega/.m at 300 K. Ferroelectric Pb(Zr/sub 0.53/Ti/sub 0.47/)O/sub 3/ (PZT) thin films have been grown on epitaxial LNO bottom electrodes by PLA method. The capacitance as well as the dielectric loss (tg/spl delta/) measurements of PZT thin film in the trilayer Ag/PZT/LNO/STO have been carried out using the HP 1615A Capacitance Bridge at room temperature. P-E hysteresis loop of this sample had been measured using the Sawyer-Tower circuit.

关键词： Optical pulses Laser ablation Temperature Transistors Dielectric thin films Dielectric loss measurement Substrates X-ray lasers programmable logic arrays Capacitance

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Technology mapping for FPGAs with complex block architectures by fuzzy logic technique

Technology mapping for FPGAs with complex block architecture...

引用

Asia and South Pacific Design Automation Conference

作者： Jun-Yong Lee E. Shragowitz Department of Computer Science University of Minnesota Minneapolis MN USA

This paper describes a technology mapper for FPGAs with the complex structure of logic blocks. Most technology mappers developed so far are not effective for such complex logic block architectures as XILINX XC4000 series. The proposed mapper applies a constructive mapping algorithm and fuzzy logic rules to balance such criteria as area, timing, routability and others. Performance of the mapper is demonstrated on the set of MCNC benchmarks.

关键词： Field programmable gate arrays Fuzzy logic Timing Tree graphs Table lookup Vegetation mapping Computer architecture Computer science programmable logic arrays Boolean functions

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