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检索条件"主题词=Programmable Logic Arrays"

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Real-time route planning for UAV based on weather threat

Real-time route planning for UAV based on weather threat

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International Conference on Remote Sensing, Environment and Transportation Engineering (RSETE)

作者： Shudao Zhou Guotao Zhu Hao Li Yanjie Wang Xiaotan Liu Institute of Meteorology People''s Liberation Army University of Science and Technology Nanjing China Dingxi China

ISBN: (纸本)9781424491728

UAVs may encouter execrable weather, terrain threat, firepower threat or task object changed while it was flying along the fixed route, a real-time route planning method was proposed. The mechanism how to solve these unexpected problems while flying was given. The rule of state conversion and pheromone updating were improved on the basis of traditional Ant Colony Algorithm(ACA). Some parameters were self-adaptive optimized, genetic operations and smoothness method were introduced in the Improved Ant Colony Algorithm(I-ACA). Two situations were simulated combined with real-time weather threat, in which target object was changed or not. Simulation results show that the real-time route planning strategy has strong ability to search real-time routes fast. It is able to solve abrupt problems well and offer real-time viable, safe and optimal routes for UAVs.

关键词： Meteorology Real time systems Planning Optimization Atmospheric modeling programmable logic arrays Computers

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The study of the instruction strategy on armored equipment major courses based on virtual reality technology

The study of the instruction strategy on armored equipment m...

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International Conference on Multimedia Technology

作者： Jian Zhang Tao Huang Kuishan Zhang Bin Li Control Engineering Department Armored Force Engineering Institute Beijing China 1st Research Room 63961 Unit People''s Liberation Army Beijing China

ISBN: (纸本)9781612847719

Aiming at the teaching problems of major courses on armored equipment, this article sets forth the instruction strategy, which sets up the instruction situation referencing the usual training task in armored and mechanized army based on desktop virtual reality system to improve the learning enthusiasm of students. The instruction strategy is executed through 'subject' combined with 'question', and is designed on three aspects: visual cognition design, interactivity design and virtual situation learning, which are aligned with the desktop virtual reality system.

关键词： Education Virtual reality Materials Control engineering programmable logic arrays IP networks Visualization

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Improvement of emission efficiency of nanocrystalline silicon planar cathodes

Improvement of emission efficiency of nanocrystalline silico...

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20th International Vacuum Nanoelectronics Conference (IVNC 2007)

作者： Hidetaka Shimawaki Yoichiro Neo Hidenori Mimura Katsuhisa Murakami Fujio Wakaya Mikio Takai Hachinohe Institute of Technology Hachinohe Japan Research Institute of Electronics Shizuoka University Hamamatsu Japan Center for Quantum Science and Technology under Extreme Conditions Osaka University Osaka Japan

A metal-oxide-semiconductor (MOS) cathode is a promising candidate as a fine electron source for applications of vacuum nanoelectronic devices, because the cathode operates at low extraction voltage, and produces uniform and highly directional emission. Furthermore, the cathode is insensitive to environment. However, the device is limited in emission current by its low efficiency of less than 1% due to the strong phonon-electron scattering in both the oxide layer and the gate electrode during traveling through the conduction band of the oxide and the gate electrode.

关键词： Silicon Cathodes Optical pulses Laser ablation programmable logic arrays Mechanical factors Semiconductor films Substrates Electron sources Electrodes

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Evolutional design of small antennas for passive UHF-band RFID

Evolutional design of small antennas for passive UHF-band RF...

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Biennial Institute of Electrical and Electronics Engineers Conference on Electomagnetic Field Computation

作者： Hidetoshi Makimura Yuta Watanabe Kota Watanabe Hajime Igarashi Graduate School of Information Science and Technology Hokkaido University

ISBN: (纸本)9781424470594

This paper presents optimal design of antennas for passive IC tags used in UHF-band radio frequency identification. To improve the performance of IC tags, the shape of the meander line antennas and planar lattice antennas are optimized using the genetic algorithm. In the optimization process, the objective function includes the terms relevant to the antenna size, gain and input impedance. The characteristics of the antennas printed on a dielectric substrate are evaluated using the moment method. The optimization results in desirable input impedance for impedance matching and miniaturizing.

关键词： Radiofrequency identification Passive RFID tags Dipole antennas Shape programmable logic arrays Lattices Dielectric substrates Impedance matching Optimization methods Genetic algorithms

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An Efficient Greedy Approach to PLA Folding

An Efficient Greedy Approach to PLA Folding

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2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008), vol.4

作者： Mayur Bubna Naresh Shenoy Santanu Chattopadhyay Department of Computer Sciences & Engineering Indian Institute of Technology Kharagpur India Department of Electronics & Electrical. Communication Engineering Indian Institute of Technology Kharagpur India

In this paper, a greedy approach for minimizing the area of a programmable logic Array (PLA) using column folding of combinational component of Finite State Machines (FSMs) is presented. Also, the row reordering problem is addressed and a simple data structure is proposed to satisfy the constraints imposed by folding of columns. Genetic algorithm based formulation has been used for state encoding which gives minimally reduced two-level PLAs. Results obtained for several MCNC benchmark circuits show area improvement of 16.7percent over NOVA[9], 53.1percent over KISS[8] and 12.3percent over STARF[7] on an average.

关键词： programmable logic arrays Encoding Genetic algorithms Costs logic design Data structures Field programmable gate arrays logic arrays Decoding Automata

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Design and Testing of a Recycled 3D Printed and Foldable Unmanned Aerial Vehicle for Remote Sensing

Design and Testing of a Recycled 3D Printed and Foldable Unm...

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International Conference on Unmanned Aircraft Systems

作者： Akif Mosaddek Hrushi K. R. Kommula Felipe Gonzalez Electrical and Aerospace Engineering Queensland University of Technology (QUT) Brisbane Robotics and Autonomous systems at the School of Electrical Engineering and Computer Science (EECS) Queensland University of Technology (QUT) Brisbane

The demand for UAVs (Unmanned Aerial Vehicles) has drastically increased within the past few years, with proven efficiency for remote sensing use. This paper analyses the feasibility of utilizing recycled plastics from bottles such as, Polyethylene Terephthalate (PET) as 3D printing filament, in order to rapidly print foldable UAV airframes for remote sensing use. Previous work has failed to effectively address the process of 3D printing UAVs with a lack of literature pertaining to the ability of 3D printing UAVs with recycled materials and the environmental effects associated with this. To address this issue, this paper presents results analyzing the material properties of commonly used 3D printing filaments with that of the recycled filament, which has proven to be effective in use for this application. This new approach in manufacturing UAVs is expected to significantly benefit the low-cost manufacturing of UAVs, reducing the time taken to obtain UAVs, expanding the operational scope of these systems all whilst reducing the detrimental effects to the environment without any loss of functionality.

关键词： Three-dimensional printing Testing Three-dimensional displays programmable logic arrays Strain Solid modeling Unmanned aerial vehicles

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Exploring in the teaching mode of intensive teaching and independent learning

Exploring in the teaching mode of intensive teaching and ind...

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International Conference on E-Business and E-Government (ICEE)

作者： Lirong Ma Xuefeng Li Liwei Liu Educational Technology Centre of Flight Fundamental Training Base Aviation University슠of Air슠Force ChangChun China Flight Fundamental Training Base Aviation University슠of Air슠Force ChangChun China College of Computer Science and Engineering Changchun University of Technology Changchun China

ISBN: (纸本)9781424486915

A completely new teaching mode emerges encompassing Intensive Teaching and Independent Learning as a result of optimizing education resources with advanced education technology in info-net environment. The new teaching mode in info-net environment is set up in this paper by means of analyzing and explaining concepts related, mutual relations and functions.

关键词： Publishing Training Management information systems programmable logic arrays Computers Multimedia communication

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ROM-Based Finite State Machine Implementation in Low Cost FPGAs

ROM-Based Finite State Machine Implementation in Low Cost FP...

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2007 IEEE International Symposium on Industrial Electronics (ISIE 2007), vol.6

作者： I. Garcia-Vargas R. Senhadji-Navarro G. Jimenez-Moreno A. Civit-Balcells P. Guerra-Gutierrez Departamento de Arquitectura y Tecnología de Computadores Universidad de Sevilla Seville Spain Departamento de Ingeniería Electrónica Universidad Politécnica de Madrid Madrid Spain

This work presents a technique for the resource optimization of input multiplexed ROM-based Finite State Machines. This technique exploits the don't care value of the inputs to reduce the memory size as well as multiplexer complexity. This technique has been applied to a publicly available FSM benchmarks and implemented in a low-cost FPGA. Results have been compared with tools supported ROM and standard logic cells implementations. In a significant number of test cases, the proposed technique is the best design alternative, both in resource requirements and speed.

关键词： Automata Costs Field programmable gate arrays Multiplexing Read only memory Random access memory programmable logic arrays Read-write memory Automatic control Digital signal processing

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Performance Enhancement and High-Level Specification of a Pipelined Processor in programmable logic

Performance Enhancement and High-Level Specification of a Pi...

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IEEE North-East Workshop on Circuits and Systems (IEEE-MWCAS'07)

作者： Naraig Manjikian Jonathan Roth Department of Electrical and Computer Engineering Queen''s University Kingston ONT Canada

This paper describes the performance enhancement of a custom pipelined processor in programmable logic, and the description of the enhanced processor with the higher-level specification syntax of a custom software tool for system implementation in hardware. Faster operation of the processor is enabled with a revised clocking scheme for the embedded memory blocks that are used for the register file and the caches. A higher-level implementation of the enhanced processor is specified with a custom software tool called QUI{sup}2VER (Queen's University Interface Integrator in VHDL for Education and Research) that generates VHDL output. Synthesis results obtained with Altera Quartus II for a Stratix chip characterize the modest overhead for the datapath modifications to support the revised clocking scheme in the enhanced processor datapath. Results from timing analysis indicate an increase in the processor clock frequency by 76% relative to the previous implementation.

关键词： programmable logic arrays programmable logic devices Clocks Registers logic devices Prototypes Pipelines Software tools Hardware Timing

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On the complexity of switch programming in fault-tolerant configurable chips

On the complexity of switch programming in fault-tolerant co...

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IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

作者： W. Shi K. Kumar F. Lombardi Computer Science University of North Texas Denton TX USA Electrical & Computer Engineering Northeastern University Boston MA USA

ISBN: (纸本)0769507190

Given a programmable chip (such as a WSI systolic array, or a field programmable gate array (FPGA)) made of equally-like configurable logic blocks (cells), the problem of programming the interconnect resources (consisting of switches) has been well studied in the literature. This process can be used for fault tolerance by logically reconfiguring the fault free cells of the array into a new array as well as to customize the FPGA by configuring it to perform the desired functions. Once the desired logical configuration has been achieved (as in the presence of faulty cells), the (programmable) switches in the interconnect resources of the array must be programmed to implement the target topology on the physical array. In this paper, we study the problem of minimizing the programming time (or cost) required for implementing this step. We show that current techniques are not likely to lead to cost optimal polynomial time algorithms, because the underlying covering problems are NPC-complete in the strong sense. The NPC-completeness is also extended to grid arrays.

关键词： Switches Fault tolerance programmable logic arrays Field programmable gate arrays logic programming logic arrays Systolic arrays Reconfigurable logic Topology Costs

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