79-83A controller providing communication between a computer and a CAMAC crate via the USB bus is described. For this purpose, the controller includes a DLP-USB245M module, which allows a programmer to work with the c...
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79-83A controller providing communication between a computer and a CAMAC crate via the USB bus is described. For this purpose, the controller includes a DLP-USB245M module, which allows a programmer to work with the controller through a virtual COM port and, at the same time, provides all the advantages of the USB standard. We consider versions of interactions of the DLP-USB module with controller registers on a programmablelogic array and on the microcontroller.
Reconfigurable Intelligent Surfaces (RIS)-assisted systems are promising technology in next-generation wireless networks, but are susceptible to spoofing attacks due to their broadcast nature. This letter reveals the ...
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Reconfigurable Intelligent Surfaces (RIS)-assisted systems are promising technology in next-generation wireless networks, but are susceptible to spoofing attacks due to their broadcast nature. This letter reveals the unique characteristics of RIS-aided multiple-input multiple-output (MIMO) systems, that improve channel entropy compared to conventional MIMO. By capitalizing on the additional paths introduced by the cascaded channel and the distinctive double-structured sparsity inherent in its virtual representation, we develop a novel channel-based physical layer authentication (PLA) approach. In particular, we construct a robust signature for authentication purposes by extracting the intrinsic RIS features of the virtual angle of arrivals and departures indices. Furthermore, the distribution of the digital signature is analyzed to derive analytical expressions for the false alarm and detection probabilities of the proposed scheme. Simulation results show that the proposed approach surpasses the limitations of previous works, with 14.89% and 72% authentication performance improvements in detection and false alarm rates, respectively.
For the convenience of construction and operation of a well-defined uniform magnetic field source, a structure of two orthogonal sheet current loops (TOSCL) is proposed. The distributions of the magnetic field uniform...
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For the convenience of construction and operation of a well-defined uniform magnetic field source, a structure of two orthogonal sheet current loops (TOSCL) is proposed. The distributions of the magnetic field uniformity inside the TOSCL are investigated. Self and mutual inductances of the TOSCL structure are studied. Physical factors influencing the current amplitudes are also discussed.
An exact analysis of the operation of the Schmitt trigger oscillator is presented and compared with previous methods of analysis. The analysis includes an exact closed-form expression for the oscillator period.
An exact analysis of the operation of the Schmitt trigger oscillator is presented and compared with previous methods of analysis. The analysis includes an exact closed-form expression for the oscillator period.
Presents a complete fault-tolerant programmablelogic array (PLA) design that includes both fault diagnosability and repairability. The proposed PLA design is capable of detecting, locating, and repairing single and m...
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Presents a complete fault-tolerant programmablelogic array (PLA) design that includes both fault diagnosability and repairability. The proposed PLA design is capable of detecting, locating, and repairing single and multiple stuck-at, bridging, and crosspoint faults. The results of this study show that the total augmented area overhead for both repair and fault diagnosis is nearly 15 to 25 percent over the original PLA, but the chip yield can be improved significantly.< >
The design is presented, in which a conventional PLA is modified by adding redundancy circuits. Three types of fault can be repaired: crosspoint, bridging, and stuck-at faults.
The design is presented, in which a conventional PLA is modified by adding redundancy circuits. Three types of fault can be repaired: crosspoint, bridging, and stuck-at faults.
The totally self-checking (TSC) concept is well established for applications in the area of online error-indication. TSC circuits can detect both transient and permanent faults. They consist of a functional circuit wi...
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The totally self-checking (TSC) concept is well established for applications in the area of online error-indication. TSC circuits can detect both transient and permanent faults. They consist of a functional circuit with encoded inputs and outputs and a checker which monitors these outputs. The TSC concept can be generalized for the functional circuits using the strongly fault-secure (SFS) concept. Here, the concept of strongly self-checking (SSC) circuits, which is a generalization from TSC circuits, is introduced. Most of the TSC circuits presented in the literature are designed at the logic gate level using the stuck-at fault model. However, this fault model is inadequate for MOS technologies. Here, it is shown that a TSC gate-level functional circuit can be implemented in the domino-CMOS technology as an SFS circuit, while a TSC gate-level checker can be implemented as an SSC checker. For the domino-CMOS implementation the fault model is enlarged to stuck-at, stuck-open, and stuck-on faults. It is shown that domino-CMOS is much more suitable for implementation of self-checking circuits than static CMOS.< >
A device independent Fastbus coupler interface has been designed which is capable of high speed operation as Fastbus master, data space slave, and limited control space slave. The design has been implemented on two di...
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A device independent Fastbus coupler interface has been designed which is capable of high speed operation as Fastbus master, data space slave, and limited control space slave. The design has been implemented on two different but plug compatible boards, one using TTL programmablelogic and featuring average latency of 185 nanoseconds and capable of cycle times of 200 nanoseconds, and the other using ECL macrocell arrays and featuring average latency of 35 nanoseconds and capable of cycle times of this order. Use of these boards in both unintelligent and intelligent Fastbus host interfaces as well as self contained Fastbus processing modules is described. This work has been and is being supported by the U. S. Department of Energy under SBIR contracts DE-ACO1-83ER80078, DE-ACO2-85ER80273, and DE-ACO2-87ER80455, and by the New York State Science and Technology Foundation under contract SBIR (86)-58.
Positron annihilation lifetime (PAL) measurements were used for observation of structural effects of temperature in polystyrene (PS), super-cross-linked polystyrene networks (CPS), and in polyimides (PI) below and in ...
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Positron annihilation lifetime (PAL) measurements were used for observation of structural effects of temperature in polystyrene (PS), super-cross-linked polystyrene networks (CPS), and in polyimides (PI) below and in the vicinity of glass-transition temperature T-g. "Vanishing" of these structural effects in the repeating cycles of the temperature controlled PAL experiments due to the slow relaxation processes in different conditions and details of chemical structure is demonstrated. Obtained results illustrate complex, dependent on thermal history, inhomogeneous character of the glass structure. In fact, structure of some polymer glasses is changing continuously. Calculations of the number density of free volume holes in these conditions are discussed. (c) 2006 Elsevier Ltd. All rights reserved.
Two of the main consequences of advances in VLSI technologies are increased cost of design and wiring. In CMOS synchronous systems, this cost is partly due to tedious synchronization of different clock phases and rout...
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Two of the main consequences of advances in VLSI technologies are increased cost of design and wiring. In CMOS synchronous systems, this cost is partly due to tedious synchronization of different clock phases and routing of these clock signals. Here, a single-phase clocking scheme that makes the design very compact and simple is described. It is shown that this scheme is general, simple, and safe. It provides a structure that can contain all components of a digital VLSI system, including static, dynamic, and precharged logic as well as memories and PLAs. Clock and data signals are presented in a clean way that makes VLSI circuits and systems well suited for design compilation.< >
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