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A 12-Gb/s DEMUX implemented with SiGe high-speed FPGA circuits

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2007年第9期15卷 1051-1054页

作者： You, Chao Guo, Jong-Ru Kraft, Russell P. Chu, Michael Goda, Bryan McDonald, John F. N Dakota State Univ Dept Elect & Comp Engn Fargo ND 58102 USA IBM Corp HSS Serial Interface Elect Hopewell Jct NY 12533 USA Rensselaer Polytech Inst Dept Elect Comp & Syst Engn Troy NY 12180 USA US Mil Acad Dept Elect Engn & Comp Sci West Point NY 10996 USA

A 7-12-Gb/s demultiplexer implemented with circuits for a high-speed field-programmable gate array (FPGA) is introduced in this paper. Since the first FPGA was released by Xilinx in 1985, FPGAs have become denser and more powerful. The first FPGA that operates in the microwave range was designed in 2000. Various methods, such as a new basic cell structure and multimode routing, are used to make that design faster and less power consuming. Sequential logic functions are analyzed and tested in this paper with a DEMUX implementation using these high-speed FPGA circuits. A chip measurement has shown that the FPGA can operate at a 12-GHz system clock when configured to perform sequential logic. A DEMUX that operates at 12 Gb/s is used here to demonstrate the potential for high-performance and low-power FPGA features.

关键词： current mode logic (CML) field-programmable gate arrays (FPGAs) programmable logic arrays silicon germanium

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Guest editors' introduction: Challenges for reliable design at the nanoscale

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IEEE DESIGN & TEST OF COMPUTERS 2005年第4期22卷 295-297页

作者： Bahar, RI Tahoori, MB Shukla, SK Lombardi, F Virginia Tech Dept Elect & Comp Engn Blacksburg VA 24061 USA Brown Univ Div Engn Providence RI 02912 USA Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA

It is with great pleasure that we introduce this special issue on Advanced Technologies and Reliable Design for Nanotechnology Systems to the IEEE Design & Test readership. We have selected four articles to cover a wide spectrum of techniques and applications for the reliable design of nanoscale systems; the techniques aim to circumvent the high defect rates and transient errors expected in advanced nanoscale technologies. Written by outstanding researchers in the field, these articles cover experimental and speculative topics. As with all special issues, these topics only represent the techniques and methodologies available today.

关键词： programmable logic arrays Uncertainty Moore's Law Fault tolerance Circuit noise Resource management Fabrication Circuit testing Iris Algorithm design and analysis

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Convex Quantization Preserves Logconcavity

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IEEE SIGNAL PROCESSING LETTERS 2022年 29卷 2697-2701页

作者： del Aguila Pla, Pol Boquet-Pujadas, Aleix Jalden, Joakim CIBM Ctr Biomed Imaging CH-1015 Lausanne Switzerland Ecole Polytech Fed Lausanne Biomed Imaging Grp CH-1015 Lausanne Switzerland KTH Royal Inst Technol Sch Elect Engn & Comp Sci Div Informat Sci & Engn S-11428 Stockholm Sweden

A logconcave likelihood is as important to proper statistical inference as a convex cost function is important to variational optimization. Quantization is often disregarded when writing likelihood models, ignoring the limitations of the physical detectors used to collect the data. These two facts call for the question: would including quantization in likelihood models preclude logconcavity? are the true data likelihoods logconcave? We provide a general proof that the same simple assumption that leads to logconcave continuous-data likelihoods also leads to logconcave quantized-data likelihoods, provided that convex quantization regions are used.

关键词： Quantization (signal) Data models Detectors Biological system modeling programmable logic arrays Semiconductor device modeling Probability density function Bayesian statistics likelihood privacy-aware data analysis 1-bit compressed sensing inverse problems

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A CONFIGURABLE ROM CIRCUIT FOR USE IN GATE arrays

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1987年第1期22卷 117-118页

作者： UEDA, M SAKASHITA, K ARAKAWA, T OKAZAKI, K ASAI, S KURAMITSU, Y LSI Research and Development Laboratory Mitsubishi Electric Corporation Limited Itami Hyogo Japan

A double word-line memory ROM (DWM-ROM) for use in gate arrays is described. It allows for an automatic layout by reducing the input pin count in the word lines by using two-step addressing. The advantage of this method has been verified by implementing a 16-bit microprocessor using an 8 K-gate array, based on a gate-isolated cell configuration, employing 1.5-/spl mu/m double-metal CMOS technology. The 16-bit /spl times/ 64-word ROM in the processor saves 30% of the transistor area due to the DWM-ROM.

关键词： Read only memory programmable logic arrays Decoding logic arrays logic testing Solid state circuits CMOS technology Very large scale integration Built-in self-test Automatic testing

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FPGA FOR FUZZY CONTROLLERS

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IEEE TRANSACTIONS ON SYSTEMS MAN AND CYBERNETICS 1995年第1期25卷 213-216页

作者： MANZOUL, MA JAYABHARATHI, D UNISYS CORP SAN JOSECA 95134

logic synthesis and hardware implementation of fuzzy controllers are introduced in this paper. The logic synthesis reduces the fuzzy controller to a set of Boolean equations. A software is specially developed for this purpose. The hardware implementation is carried out using Field programmable Gate arrays (FPGAs). A speed of over 50 M FLIPS is achieved. The speed is independent of the number of rules of the fuzzy controller.

关键词： Field programmable gate arrays Fuzzy control Fuzzy logic Hardware Equations programmable logic arrays Table lookup Fuzzy sets Boolean functions Fuzzy systems

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Improvement of Electret Properties of Polylactide by Loading Mineral Fillers

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IEEE TRANSACTIONS ON DIELECTRICS AND ELECTRICAL INSULATION 2022年第3期29卷 784-787页

作者： Galikhanov, Mansur Guzhova, Alina Zagidullina, Inna Kazan Natl Res Technol Univ Dept Proc Technol Polymers & Composite Mat Kazan 420015 Russia Kazan Natl Res Technol Univ Dept Foreign Languages Profess Commun Kazan 420015 Russia

The article describes the effect of fine mineral fillers (aerosil, bentonite, mica, and talc) on the properties of electret materials based on polylactide. Compositions of the polymer with 4% fillers content showed the best performances. Loading of the fillers results in a slight increase of specific volume resistivity of the samples. IR spectroscopy and differential scanning calorimetry show no significant change in chemical structure and glass transition temperature and flow (melting) point of the filler-loaded polylactide. Addition of fillers reduces melt flow index (MFI) and elongation at a break with almost no change in ultimate tensile strength.

关键词： Electrets Plastics programmable logic arrays Packaging Loading Charge carriers Electric potential Aerosil bentonite corona electret mica polylactide talc

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A NEW TESTING METHOD FOR EEPLA

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1994年第7期13卷 935-939页

作者： RAJSUMAN, R CASE WESTERN RESERVE UNIV DEPT ELECT ENGN & APPL PHYSCLEVELANDOH 44106

A testing method for EEPLA's is presented. The method requires small amount of extra hardware and provides complete fault coverage. This method exploits the fact that each crosspoint can be reprogrammed in EEPLA. To our knowledge, this is the first algorithmic test method applicable to EEPLA's. In the proposed approach, all single and multiple crosspoint faults, stuck-at faults, and bridging faults are detectable. The test set is simple and is easy to derive.

关键词： Testing Switches programmable logic arrays Hardware Circuit faults Fault detection logic arrays Fuses Cost function logic design

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Tailor-Made Stereoblock Copolymers of Poly(lactic acid) by a Truly Living Polymerization Catalyst

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JOURNAL OF THE AMERICAN CHEMICAL SOCIETY 2016年第37期138卷 12041-12044页

作者： Rosen, Tomer Goldberg, Israel Venditto, Vincenzo Kol, Moshe Tel Aviv Univ Sch Chem IL-69978 Tel Aviv Israel Univ Salerno Dipartimento Chim & Biol Via Giovanni Paolo 2 132 I-84084 Salerno Italy

Poly(lactic acid) (PLA) is a biodegradable polymer prepared by the catalyzed ring opening polymerization of lactide. An ideal catalyst should enable a sequential polymerization of the lactide enantiomers to afford stereoblock copolymers with predetermined number and lengths of blocks. We describe a magnesium based catalyst that combines very high activity with a true-living nature, which gives access to PLA materials of unprecedented microstructures. Full consumption of thousands of equivalents of L-LA-within minutes gave PLLA of expected molecular weights and narrow molecular weight distributions. Precise PLLA-b-PDLA diblock copolymers having block lengths of up to 500 repeat units were readily prepared within 30 min, and their thermal characterization revealed a stereocomplex phase only with very high melting transitions and melting enthalpies. The one pot sequential polymerization was extended up to precise hexablocks having "dialed-in" block lengths.

关键词： BLOCK LENGTH Living polymerization programmable logic arrays lactic acid Molecular weights Catalysts MELT TRANSITION poly(lactic acid) Copolymers block copolymers biodegradable polymer

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SYNTHESIS FOR PATH DELAY-FAULT TESTABILITY VIA TAUTOLOGY-BASED UNTESTABILITY IDENTIFICATION AND FACTORIZATION

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1995年第12期14卷 1470-1479页

作者： FUCHS, K Siemens Mobile Radio Networks Munich Germany

An area efficient synthesis procedure targeting complete robust path delay fault testability (RPDFT) of scan-based circuits is described, It includes an efficient untestability identification algorithm for two-level and multilevel circuits. The implementation of the algorithm uses tautology checking instead of test pattern generation (TPG) resulting in a speed-up factor of 5 in comparison to today's fastest TPG methods. Exploiting that untestability identification capability, factorization is improved to first combining only those product terms in which the same literal is untestable and checking whether this eliminates the untestable fault. If not, cardinality matching is used to add the best-suited term that removes the untestable fault. Our method has been found to give better results in terms of RPDFT and area than reported before, In contrast to previously published papers, we found that technology mapping using tree covering does not always preserve RPDFT.

关键词： Delay Fault diagnosis Circuit testing Circuit faults Circuit synthesis Robustness programmable logic arrays Test pattern generators Paper technology

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FIELD programmable ANALOG ARRAY BASED ON MOSFET TRANSCONDUCTORS

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ELECTRONICS LETTERS 1992年第1期28卷 28-29页

作者： LEE, EKF GULAK, PG Dept. of Electr. Eng. Toronto Univ. Ont. Canada

An area efficient and parasitic insensitive technique for the implementation of a field programmable analogue array is proposed. The connections between configurable analogue blocks are realised using MOSFET transconductors. The conductance is controlled by varying the gate voltages defined by a multivalued memory system or external/internal signals.

关键词： programmable logic arrays SEMICONDUCTOR DEVICES AND MATERIALS FIELD-EFFECT TRANSISTORS logic DEVICES

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