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AN FPGA FOR IMPLEMENTING ASYNCHRONOUS CIRCUITS

IEEE DESIGN & TEST OF COMPUTERS 1994年第3期11卷 60-69页

作者： HAUCK, S BURNS, S BORRIELLO, G EBELING, C University of Washington USA

Though FPGAs are a dominant implementation medium for digital circuits, they do not support asynchronous circuits. This is a significant problem because many aspects of glue logic and communication interfaces involve asynchronous elements, or require the interconnection of synchronous components operating under independent clocks. The authors describe the Montage FPGA, which explicitly supports asynchronous circuit implementation, and its mapping software.

关键词： Field programmable gate arrays Asynchronous circuits Hazards programmable logic devices Routing Delay programmable logic arrays logic devices logic design logic circuits

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A LOG-EXP still image compression chip design

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IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 1999年第3期45卷 812-819页

作者： Huang, SC Chen, LG Natl Taiwan Univ Dept Elect Engn Taipei 10764 Taiwan

In this paper, a fully pipelined single chip is proposed for the LOG-EXP still image compression. The design of the LOG-EXP image compression system focus on the high compression ratio of the complex texture (e.g. benchmark image baboon) and high quality image, especially for the PSNR requirement above 36. In comparison with the JPEG compression result (bpp = 0.99 and PSNR = 26.9), this compression algorithm uses less bpp (bpp = 0.87) to get higher image quality (PSNR = 36.38) for the benchmark image baboon. The entire LOG-EXP image compression system can be implemented on a single chip to yield a clock rate of 175 MHz which allow an input rate of 30 frames per second for 1024 x 1024 color images.

关键词： Image coding Chip scale packaging Transform coding PSNR programmable logic arrays Image quality Multimedia systems Videoconference Video compression Pixel

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Transparent bionanocomposites with improved properties prepared from acetylated bacterial cellulose and poly(lactic acid) through a simple approach

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GREEN CHEMISTRY 2011年第2期13卷 419-427页

作者： Tome, Liliana C. Pinto, Ricardo J. B. Trovatti, Eliane Freire, Carmen S. R. Silvestre, Armando J. D. Pascoal Neto, Carlos Gandini, Alessandro Univ Aveiro CICECO P-3810193 Aveiro Portugal Univ Aveiro Dept Chem P-3810193 Aveiro Portugal

The preparation and characterization of biocomposite materials with improved properties based on poly(lactic acid) (PLA) and bacterial cellulose, and, for comparative purposes, vegetal cellulose fibers, both in their pristine form or after acetylation, is reported. The composite materials were obtained through the simple and green mechanical compounding of a PLA matrix and bacterial cellulose nanofibrils (or vegetable fibers), and were characterized by TGA, DSC, tensile assays, DMA, SEM and water uptake. The bionanocomposites obtained from PLA and acetylated bacterial cellulose were particularly interesting, given the considerable improvement in thermal and mechanical properties, as evidenced by the significant increase in both elastic and Young moduli, and in the tensile strength (increments of about 100, 40 and 25%, respectively) at very low nanofiller loadings (up to 6%). These nanocomposites also showed low hygroscopicity and considerable transparency, features reported here for the first time.

关键词： Cellulose Composites programmable logic arrays ACETYLATION cellulose microfibrils simplicial approximation Cellulose fibers Vegetable fibers poly(lactic acid)

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BIPARTITE FOLDING AND PARTITIONING OF A PLA

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1984年第3期3卷 191-199页

作者： EGAN, JR LIU, CL UNIV ILLINOIS DEPT COMP SCIURBANAIL 61801

A more restricted definition of a PLA folding is introduced, which is called bipartite folding. The additional constraints of a bipartite folding force the resulting PLA to have a more uniform structure. This structure of a column bipartite folding is then exploited when subsequently folding the rows of the PLA. A column bipartite folding creates fewer constraints upon the ability to fold the rows of the resulting PLA; thus there is a greater probability of folding the rows. Obviously, the more columns and rows of the PLA that are folded, the less area that is needed to implement the PLA. An efficient branch and bound algorithm is presented which finds an optimal bipartite folding of a PLA. Our experimental results shows that the size of an optimal bipartite folding compares favorably to the size of a folding discovered by a heuristic algorithm. This algorithm can also be used to partition a large PLA into smaller PLA's.

关键词： programmable logic arrays Very large scale integration Partitioning algorithms Algorithm design and analysis logic arrays Circuits logic design Heuristic algorithms Complexity theory

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SEGMENTED CHANNEL ROUTING

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1993年第1期12卷 79-95页

作者： ROYCHOWDHURY, VP GREENE, JW ELGAMAL, A ACTEL CORP SUNNYVALECA STANFORD UNIV INFORMAT SYST LABSTANFORDCA 94305 COLUMBIA UNIV DEPT CHEMNEW YORKNY 10027

Novel problems concerning routing in a segmented routing channel are introduced. These problems are fundamental to routing and design automation for field programmable gate arrays (FPGA's), a new type of electrically programmable VLSI. The first known theoretical results on the combinatorial complexity and algorithm design for segmented channel routing are presented. It is shown that the segmented channel routing problem is in general NP-complete. Efficient polynomial time algorithms for a number of important special cases are presented.

关键词： Routing Switches Field programmable gate arrays Wiring programmable logic arrays Design automation Very large scale integration Algorithm design and analysis Polynomials Heuristic algorithms

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A 20-B DYNAMIC-RANGE FLOATING-POINT DATA ACQUISITION-SYSTEM

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 1991年第1期38卷 10-14页

作者： CHEN, F CHEN, CS Electrical Engineering Department University of Akron Akron OH USA

This paper describes the design and engineering of a floating-point data-acquisition system. The system has both automatic gain and software-programmable gain adjustment features. In automatic gain adjustment mode, the gain is set automatically dependent on the input amplitude so that the full conversion resolution is maintained irrespective of the signal dynamic range. A high-speed flash ADC with an approximately 35-ns conversion time is used to quickly convert the signal into 8-b data. A programmable array logic (PAL) then transfers this 8-b digital data into 12-b information for setting the gain of the variable-gain amplifier. Depending on this PAL output bit pattern, the amplifier gain is set at one of the nine settings-1, 2, 4, 8, 16, 32, 64, 128, and 256. The nine settings are representable as a 4-b gain information. With this gain selection arrangement, the amplifier output is always between half and full scale of the allowable range, which means that the conversion resolution of the subsequent sampling ADC is at least 11 b. The amplifier gain settings are all powers of 2;thus, the normalization of the digitized data requires only bit shifting operation and no complex software division. The gain information together with the 12-b sampling ADC output increases the dynamic range to 20 b. The software package includes commands needed for the system initiation, automatic or nine software programmable gain selection, sampling and conversion, and data normalization. The system has applications in sampling and converting a one-shot burst-type signal with full resolution throughout the wide dynamic range of the signal.

关键词： Data acquisition Dynamic range programmable logic arrays Sampling methods Maintenance engineering Data engineering Design engineering Signal resolution Operational amplifiers Power amplifiers

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Evolutionary design and adaptation of high performance digital filters within an embedded reconfigurable fault tolerant hardware platform

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SOFT COMPUTING 2004年第5期8卷 307-317页

作者： Hounsell, BI Arslan, T Thomson, R Univ Edinburgh Sch Engn & Elect Edinburgh EH9 3JL Midlothian Scotland

Finite impulse response filters (FIRs) are crucial devices for robust data communication and manipulation. Multiplierless filters have been shown to produce high performance systems with fast signal processing and reduced area. Furthermore, the distributed architecture inherent in multiplierless filters makes it a suitable candidate for fault tolerant design. Alternative approaches to the design of fault tolerant systems have been proposed using evolutionary algorithms (EAs) and the concept of evolvable hardware (EHW). This paper presents an evolvable hardware platform for the automated design and adaptation of multiplierless digital filters. Filters are realised within a dedicated programmable logic array (PLA) based on the Primitive Operator Filter design principle. The platform employs a genetic algorithm to autonomously configure the PLA for a given set of coefficients. The ability of the platform to adapt to increasing numbers of faults was investigated through the "evolution" of a 31-tap low-pass FIR filter. Results show that the functionality of filters evolved on the PLA was maintained despite an increasing number of faults covering up to 25% of the PLA area. Additionally, three PLA initialisation methods were investigated to ascertain which produced the fastest fault recovery times. It was shown that seeding a population of random configuration-strings with the best configuration currently obtained resulted in a 6 fold increase in fault recovery speed over other methods investigated.

关键词： genetic algorithms evolvable hardware robust hardware fault tolerant programmable logic arrays PLAs finite impulse response filters FIR filters

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Lack of Metabolic Activation and Predominant Formation of an Excreted Metabolite of Nontoxic Platynecine-Type Pyrrolizidine Alkaloids

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CHEMICAL RESEARCH IN TOXICOLOGY 2014年第1期27卷 7-16页

作者： Ruan, Jianqing Liao, Cangsong Ye, Yang Lin, Ge Chinese Univ Hong Kong Fac Med Sch Biomed Sci Hong Kong Hong Kong Peoples R China Chinese Acad Sci Shanghai Inst Mat Med Joint Res Lab Promoting Globalizat Tradit Chinese Beijing 100864 Peoples R China Chinese Univ Hong Kong Hong Kong Hong Kong Peoples R China Chinese Acad Sci Shanghai Inst Mat Med State Key Lab Drug Res Beijing 100864 Peoples R China Chinese Acad Sci Shanghai Inst Mat Med Nat Prod Chem Dept Beijing 100864 Peoples R China

Pyrrolizidine alkaloid (PA) poisoning is well-known because of the intake of PA-containing plant-derived natural products and PA-contaminated foodstuffs. Based on different structures of the necine bases, PAs are classified into three types: retronecine, otonecine, and platynecine type. The former two type PAs possessing an unsaturated necine base with a 1,2-double bond are hepatotoxic due to the P450-mediated metabolic activation to generate reactive pyrrolic ester, which interacts with cellular macromolecules leading to toxicity. With a saturated necine base, platynecine-type PAs are reported to be nontoxic and their nontoxicity was hypothesized to be due to the absence of metabolic activation;however, the metabolic pathway responsible for their nontoxic nature is largely unknown. In the present study, to prove the absence of metabolic activation in nontoxic platynecine-type PM, hepatic metabolism of platyphylline (PLA), a representative platynecine-type PA, was investigated and directly compared with the representatives of two toxic types of PAs in parallel. By determining the pyrrolic ester-derived glutathione conjugate, our results confirmed that the major metabolic pathway of PLA did not lead to formation of the reactive pyrrolic ester. More interestingly, having a metabolic rate similar to that of toxic PAs, PLA also underwent oxidative metabolisms mediated by P450s, especially P450 3A4, the same enzyme that catalyzes metabolic activation of two toxic types of PAs. However, the predominant oxidative dehydrogenation pathway of PLA formed a novel metabolite, dehydroplatyphylline carboxylic acid, which. was water-soluble, readily excreted, and could not interact with cellular macromolecules. In conclusion, our study confirmed that the saturated necine bases determine the absence of metabolic activation and thus govern the metabolic pathway responsible for the nontoxic nature of platynecine-type PAS.

关键词： programmable logic arrays Pyrrolizidine Alkaloids Metabolic activation Metabolic Pathways protactinium

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SHORTENING THE DESIGN CYCLE FOR programmable logic DEVICES

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IEEE DESIGN & TEST OF COMPUTERS 1992年第4期9卷 40-50页

作者： KELEM, SH SEIDEL, JP XILINX INC EPLD SOFTWARE GRPSAN JOSECA 95124

X-BLOX, a software tool for mapping architecture-independent designs to field-programmable gate arrays (FPGAs), is described. X-BLOX synthesizes a delay- and area-efficient logic-level design from an input specification consisting of a network of generic modules. The tool automatically propagates partial data type specification, performs architecture-specific design optimization, and performs context-dependent module synthesis.

关键词： logic design programmable logic arrays programmable logic devices logic devices Application specific integrated circuits Circuit synthesis Design methodology Hardware design languages Packaging machines logic circuits

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Thermal characteristics of polylactic acid/wheat gluten blends

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JOURNAL OF FOOD QUALITY 2006年第3期29卷 266-281页

作者： Mohamed, Abdellatif A. Gordon, Sherald H. Carriere, Craig J. Kim, Sanghoon USDA ARS Natl Ctr Agr Utilizat Res Peoria IL 61604 USA

The interaction between polylactic acid (PLA) and wheat gluten (gluten) has been studied using differential scanning calorimetry (DSC), thermogravimetric analysis (TGA), Fourier transform infrared (FTIR) spectroscopy, X-ray diffraction and phase contrast microscope. The primary DSC thermogram of gluten showed one glass transition (Tg) at 63C. Neat (pure) PLA also showed a Tg around the same temperature range followed by crystallization (Cry) and a melting (Mel) transition. Different PLA : gluten blends (20:80, 50:50, 80:20) showed a Tg followed by PLA Cry and immediate Mel transitions. However, subsequent heating-cooling cycling of the blend demonstrated a decrease in PLA Cry and Mel transitions and the appearance of a second Tg. The presence of gluten reduced the number of cycles needed to change PLA Cry structure to mostly amorphous. The low PLA Cry indicates an interaction between the two polymers. The TGA data showed slower PLA degradation compared with gluten, where 10% was degraded at 316C while 10% of the gluten degraded at 254C. Solid-state FTIR showed that amide I and II peaks significantly decreased signifying gluten-heat degradation. A strong peak, corresponding to ester formation between gluten and hydrolyzed gluten molecules, appeared at 1750/cm. The esterification increased in the presence of PLA. The phase contrast microscope demonstrated that the melting of PLA starts at 150C, which means that the continuous phase between 150 and 250C was the melted PLA. At 220C, gluten formed a thin layer;and at about 245C, it aggregated.

关键词： transfer gate Phase-Contrast Microscopy TGA data programmable logic arrays Glutens

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