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MODERN NUCLEAR GENERATING PLANT CONTROLS - AN INTEGRATED APPROACH

IEEE TRANSACTIONS ON POWER APPARATUS AND SYSTEMS 1980年第6期99卷 2338-2350页

作者： LONGENECKER, CL KELLY, DK WILLEMS, VH Gilbert Commonwealth Inc. Reading PA USA

An integrated approach to plant control and monitoring has been applied to the development of the Gilbert/Commonweal-th reference nuclear plant design. The purpose of this paper is to describe this approach and to detail its effects on the plant design. Areas discussed include the development of the control and monitoring philosophy and the application of solid state control systems, programmable logic controls, and plant data acquisition and display computers.

关键词： Nuclear power generation Control systems Computer displays Computerized monitoring Application software Solid state circuits programmable logic arrays programmable logic devices programmable control Data acquisition

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WIRE-ROUTING MACHINES - NEW TOOLS FOR VLSI PHYSICAL DESIGN

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PROCEEDINGS OF THE IEEE 1983年第1期71卷 57-65页

作者： HONG, SJ NAIR, R IBM Thomas J. Watson Research Center Yorktown Heights NY USA

Interconnection of components in a VLSI chip is becoming an increasingly complex problem. In this paper we examine the complexity of the wire routing process and discuss several new approaches to solving the problem using a parallel system architecture. The machines discussed range from compact systems for highly specialized applications to more general designs suited for broader applications. The process speedup due to parallelism and the cost advantage due to the use of large numbers of identical VLSI parts make these new machines practical today.

关键词： Very large scale integration Wire Wiring Routing Process design Integrated circuit interconnections logic design logic testing Polynomials programmable logic arrays

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MULTI-AREA NETWORK MODELING FOR POWER POOLS

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IEEE TRANSACTIONS ON POWER APPARATUS AND SYSTEMS 1976年第2期95卷 586-594页

作者： HAPP, HH NOUR, NE GE POWER SYST ENGN COURSESCHENECTADYNY 12301 NEW YORK POWER POOL SCHENECTADYNY

A power pool consists of a number of interconnected electric utilities referred to as pool members that coordinate their operations to improve reliability and produce an optimal allocation of generation. The coordination takes place by recognizing the pool as a multiarea system and allocating generation for each area separately, then combining the individual allocations to form a total allocation on the pool level. Mathematical models are required for the allocation of generation both on the pool level and on the area level. The paper presents a procedure of creating such models, applicable to both off-line studies and real time operations, and represents an extension of work reported earlier by the authors.

关键词： Power markets Power system modeling Impedance Load flow Voltage Power system interconnection Tin Transportation Time of arrival estimation programmable logic arrays

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Authentication for Satellite Communication Systems Using Physical Characteristics

IEEE OPEN JOURNAL OF VEHICULAR TECHNOLOGY

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IEEE OPEN JOURNAL OF VEHICULAR TECHNOLOGY 2023年 4卷 48-60页

作者： Abdrabou, Mohammed Gulliver, T. Aaron Univ Victoria Dept Elect & Comp Engn Victoria BC V8W 2Y2 Canada

Satellite communication networks have gained a lot of attention recently as a solution to mitigate the limitations of terrestrial networks such as stability and coverage. However, integrating satellite and terrestrial networks makes the system more vulnerable to spoofing attacks. Thus, robust and effective authentication is required. Physical layer authentication (PLA) has emerged as an alternative paradigm that uses physical characteristics to achieve authentication. In this paper, PLA is proposed for low earth orbit (LEO) satellites using the Doppler frequency shift (DS) and received power (RP) characteristics. Hypothesis testing using a threshold or machine learning (ML) is considered to discriminate between legitimate and illegitimate satellites. For ML, a one-class classification support vector machine (OCC-SVM) is employed which uses training data from only legitimate users. The performance is evaluated using real satellite data from the system tool kit (STK). Results are presented which show that the authentication rate (AR) with DS is higher than with RP at low elevation angles for both schemes, but is higher with RP at high elevation angles. Further, the ML authentication scheme provides a higher AR than the threshold scheme for a small percentage of the training data considered as outliers, but at larger percentages the OR threshold scheme is better.

关键词： Satellites Authentication Training data Low earth orbit satellites programmable logic arrays Machine learning Physical layer Doppler frequency shift physical layer authentication received power vertical heterogeneous network space network machine learning

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ADC FASTBUS 12 BITS-96 CHANNELS (ID-F6829)

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 1985年第4期32卷 1339-1340页

作者： BELLEMAIN, A AUGE, E HEUSSE, P Laboratoire de l'Accélérateur Linéaire Université de Paris-Sud Orsay France

The 96 input channels are multiplexed to six (12 bits) converters in such a way that adjacent channels are driven to different chips. The maximum conversion time is 65 μs. Common analog threshold for zero suppression is available with possible choice of neighbours to be converted. The threshold action can be disabled by external input command (or CSR # 0 status). S.R. and broadcasts are implemented.

关键词： Fastbus Broadcasting logic testing Latches Field programmable gate arrays programmable logic arrays Multiplexing Impedance matching Hardware Physics

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COMPUTER-AIDED MINIMIZATION PROCEDURE FOR BOOLEAN FUNCTIONS

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1986年第2期5卷 303-304页

作者： BISWAS, NN Department of Electrical Communication Engineering Indian Institute of Science Bangalore India

This paper describes the salient features of CAMP, a Computer Aided Minimization Procedure for single Boolean functions. The procedure is a divide and conquer algorithm, in which the essential prime implicants are first found, and then the best cover among the selective prime implicants are chosen. A significant feature of the algorithm is that the selection of the most suitable selective prime implicant to cover a minterm is based upon the information associated with the degree and direction of adjacency of the minterm itself. The generation of the complement of the function is not a requirement of the algorithm. The procedure has been implemented in a 250 line Fortran program. For shallow functions consisting mainly of essential prime implicants (EPI's) and a few selective prime implicants (SPI's), CAMP produces the exact or near minimal sum of product form. For dense functions consisting of a large number of interconnected cyclic SPI chains, a good minimal solution is obtained by minimizing the complementary function.

关键词： Boolean functions Minimization methods programmable logic arrays Very large scale integration Page description languages Integrated circuit interconnections logic design logic circuits Economic indicators Design automation

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Low power adiabatic programmable logic array with APDL-2

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ELECTRONICS LETTERS 2003年第21期39卷 1501-1502页

作者： Yang, WJ Zhou, Y Lau, KT Nanyang Technol Univ Sch Elect & Elect Engn Ctr Integrated Circuits & Syst Singapore 639798 Singapore

A novel low power programmable logic array (PLA) structure based on adiabatic switching is presented. Simulation results show that the power consumption is similar to that of the adiabatic pseudo-domino logic (APDL) PLA, but while standard transistor sizing for the isolation transistor can be applied, in APDL PLA this transistor was designed with a larger width.

关键词： programmable logic arrays low-power electronics CMOS logic circuits lowpower PLA structure low power programmable logic array adiabatic switching power consumption adiabatic pseudo-domino logic circuit structure standard sized isolation transistor APDL-2

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PLA DESIGN FOR SINGLE-CLOCK CMOS

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1992年第8期27卷 1211-1213页

作者： BLAIR, GM Department of Electrical Engineering University of Edinburgh Edinburgh UK

The circuit implementation of a CMOS programmable logic array (PLA) is described for use with a single-phased clock, combining both dynamic and pseudo-NMOS design styles. Compact layout and high speed of operation is ... 详细信息

关键词： High-speed operation programmable logic arrays timing diagram CIRCUIT DESIGN Complementary Metal Oxide Semiconductor single phase Power dissipation High speed Surgery circuit layout

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Phase Compensation Using Multipeak PSVT Algorithm in Coherent Doppler Tomography

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IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS 2021年第8期31卷 969-972页

作者： Crawley, Brent R. Baum, Thomas C. Nicholson, Kelvin J. Ghorbani, Kamran RMIT Univ Melbourne Vic 3001 Australia Def Sci & Technol Grp Melbourne Vic 3207 Australia RMIT Univ Sch Engn Melbourne Vic 3001 Australia

Presented in this letter is an improved version of the point scatterer vector tracking (PSVT) method for noise estimation in microwave coherent Doppler tomography (CDT). This new process of multipeak PSVT (MP-PSVT) significantly improves the quality of the tomogram given a noisy dataset. Phase shifts caused by positional displacements between the microwave source and center of rotation are compared against multiple isotropic scatterers placed within an image plane. Correlation between a subset of estimated shifts is then used to formulate a singular noise function. This noise function is used to deembed the original dataset thereby compensating for all phase errors. The example performed in this letter leads to a 0.91 correlation coefficient in the linear regression model containing the estimated noise and the applied noise. This new MP-PSVT approach significantly outperforms the original PSVT method.

关键词： programmable logic arrays Synthetic aperture radar Microwave imaging Tomography Microwave theory and techniques Radar tracking Noise measurement Chirp-Z transform (CZT) coherent Doppler tomography (CDT) nondestructive evaluation (NDE) point scatterer vector tracking (PSVT) synthetic aperture radar (SAR)

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ON-CHIP HIGH-VOLTAGE GENERATION IN MNOS INTEGRATED-CIRCUITS USING AN IMPROVED VOLTAGE MULTIPLIER TECHNIQUE

引用

IEEE JOURNAL OF SOLID-STATE CIRCUITS 1976年第3期11卷 374-378页

作者： DICKSON, JF PLESSEY CO LTD ALLEN CLARK RES CTR TOWCESTERNORTHAMPTONSHIRENGLAND

An improved voltage multiplier technique has been developed for generating +40 V internally in p-channel MNOS integrated circuits to enable them to be operated from standard +5- and -12-V supply rails. With this technique, the multiplication efficiency and current driving capability are both independent of the number of multiplier stages. A mathematical model and simple equivalent circuit have been developed for the multiplier and the predicted performance agrees well with measured results. A multiplier has already been incorporated into a TTL compatible nonvolatile quad-latch, in which it occupies a chip area of 600 /spl mu/m/spl times/240 /spl mu/m. It is operated with a clock frequency of 1 MHz and can supply a maximum load current of about 10 /spl mu/A. The output impedance is 3.2 M/spl Omega/.

关键词： Voltage programmable logic arrays Nonvolatile memory Solid state circuits Large scale integration logic arrays Laboratories Frequency Conferences CMOS integrated circuits

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