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International Symposium on Multiple-Valued logic

作者： T. Utsumi N. Kamiura Y. Hata K. Yamato Mitsubishi Electric Corporation Limited Chiyoda Tokyo Japan Department of Computer Engineering Himeji Institute of Technology Himeji Japan

A universal literal is a single-variable function and has an ability to manipulate more information than a set literal. The array size therefore could be eliminated by using universal literal generators (ULGs for short) in programmable logic arrays (PLAs), compared to PLAs with set literals. This paper discusses what operator is the most suitable in the term of eliminating the array size. We find four solutions as the good operator structures to eliminate the array size. A speculation of the upper bound of the array sizes is shown. Experiments are also done for randomly generated functions and some arithmetic functions. The experimental results show that the MAX-of-TPRODUCT form PLAs require the smallest array size.

关键词： programmable logic arrays Upper bound Arithmetic Very large scale integration logic circuits logic design Costs Propagation delay Power dissipation Signal generators

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The structure of complete test sets for programmable logic arrays

The structure of complete test sets for programmable logic a...

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European Test Conference

作者： E.I. Goldberg Y.A. Novikov Belarusian Academy of Sciences Minsk Belarus

A new approach to complete testing of a PLA without any auxiliary facilities is presented. PLA testability is provided by the exact minimization of the PLA in the number of product lines. A theorem about the structure of a complete test set detecting all testable single and multiple crosspoint faults in such a minimal PLA is presented. It formulates the three conditions to which the complete test set satisfies. A technique for constructing complete test sets is discussed.< >

关键词： programmable logic arrays logic testing Fault detection Very large scale integration Cybernetics logic design Degradation Decoding

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Enhancing random-pattern coverage of programmable logic arrays via masking technique

Enhancing random-pattern coverage of programmable logic arra...

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IEEE International Test Conference

作者： H. Fujiwara O. Fujisawa K. Hikone Department of Electronics and Communications Meiji University Kawasaki Japan

A testable design is presented of programmable logic arrays (PLAs) with high fault coverage for random test patterns. The proposed design is realized with low area overhead by adding two mask arrays to the AND and OR arrays of the PLA. To clarify the effect of the masking technique, an experiment was performed in which eight large PLAs were modified by adding various sizes of mask arrays, and then performing fault simulation with random patterns for those random-pattern test coverage curves. It was found that fault coverage could be significantly enhanced by the proposed masking technique with very low area overhead.< >

关键词： programmable logic arrays Circuit faults Circuit testing Built-in self-test logic testing Electronic equipment testing Decoding logic arrays logic design Very large scale integration

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On-chip testing of embedded programmable logic arrays

On-chip testing of embedded programmable logic arrays

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IEEE Pacific Rim Conference on Communications, Computers and Signal Processing

作者： E. Macii T. Wolf Department of Electrical and Computer Engineering University of Colorado Boulder CO USA Dip. di Automatica e Informatica Politecnico di Torino Torino Italy Department of Electrical Engineering University of California Los Angeles CA USA

The authors consider the problems associated with on-chip testing of programmable logic arrays (PLAs) which are deeply embedded in VLSI systems. A detailed summary of the built-in logic block observer (BILBO) approach to embedded PLA testing is given. Then, an innovative method for on-chip testing, which makes use of the input/output registers of the PLA as test aids, is presented. This method is less area-consuming than the traditional BILBO technique.< >

关键词： programmable logic arrays logic testing Circuit testing System testing Very large scale integration Test pattern generators Built-in self-test Registers logic design Automatic testing

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Implementation of fault-tolerant sequential circuits using programmable logic arrays

Implementation of fault-tolerant sequential circuits using p...

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Great Lakes Symposium on VLSI

作者： N. Misra A.K. Goel Department of Electrical Engineering Michigan Technological University Houghton MI USA

An efficient implementation procedure has been developed for the realization of sequential circuits using PLAs. The synthesis procedure is simple and based on a heuristic approach. Synchronous sequential circuits which have been widely used in digital computers over the years can be easily implemented in a single chip layout. One of the major advantages of this method is the reduction in chip area in terms of the fusible links blown to realize the state machine using PLAs.< >

关键词： programmable logic arrays Sequential circuits Fault tolerance Equations logic design Silicon Timing Clocks Hazards logic arrays

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The Effect of Device Parameter Variations on programmable Majority logic arrays

The Effect of Device Parameter Variations on Programmable Ma...

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IEEE Conference on Nanotechnology

作者： Harika Manem Kiran Dadhirao Garrett S. Rose Department of Electrical and Computer Engineering Polytechnic University Brooklyn NY USA

ISBN: (纸本)9781424421039

Molecular scale electronics has become an attractive alternative and even extension to existing microscale technologies as they migrate to the nanoscale. With recent research in the field of molecular and nano electronics, devices such as switches and resonant tunneling diodes (RTD) have been developed which exhibit properties such as rectification, hysteresis and negative differential resistance (NDR). These devices have been utilized to realize circuits that can implement both memory and logic structures. This work revolves around the robustness of these nanoscale devices when employed in nanoelectronic programmable majority logic arrays (PMLA), programmable logic circuits based on majority logic resulting from NDR. We also show the results of corner analysis of the circuit's performance under parameter variations, and describe the behavior requirements of the aforementioned molecular devices, especially those of molecular switches, for the system to function efficiently.

关键词： Nanoscale devices Switches programmable logic arrays Junctions Integrated circuit modeling logic arrays Heating

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Low-power programmable-logic cell arrays using nonvolatile complementary atom switch

Low-power programmable-logic cell arrays using nonvolatile c...

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IEEE International Symposium on Quality Electronic Design

作者： M. Miyamura T. Sakamoto M. Tada N. Banno K. Okamoto N. Iguchi H. Hada Low-power Electronics Association & Project (LEAP) Tsukuba Ibaraki Japan

programmable-logic cell that utilizes complementary atom switch (CAS) is fabricated using 65 -nm node CMOS process. A 16-bit ALU is implemented and demonstrated on a 24×24 programmable-logic cell array including 645kbit CAS for both routing switches and configuration memories. Comparing the conventional cell design using CMOS routing multiplexer (MUX), the proposed programmable-logic cell array performs 60% active power saving and 3 times faster operation.

关键词： Computer architecture Switches Microprocessors Routing CMOS integrated circuits programmable logic arrays Programming

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ARCHITECTURE OF FIELD-programmable GATE arrays - THE EFFECT OF logic BLOCK FUNCTIONALITY ON AREA EFFICIENCY

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1990年第5期25卷 1217-1225页

作者： ROSE, J FRANCIS, RJ LEWIS, D CHOW, P Department of Electrical Engineering University of Toronto

This paper examines the relationship between the function- ality of a field-programmable gate array (FPGA) logic block and the area required to implement digital circuits using that logic block. This investigation is done experimentally by implementing a set of industrial circuits as FPGA s using CAD tools for technology mapping, placement, and routing. Using a simple model of the interconnection and logic block area, a range of programming technologies (the method of FPGA customization) is explored. The experiments are based on logic blocks that use lookup tables for implementing combinational logic. Results indicate that the best number of inputs to use (a measure of the block s functionality) is between three and four, and that a D flip-flop should be included in the logic block. These results are largely independent of the programming technology. More generally, it was observed that the area efficiency of a logic block depends not only on its functionality but on the average number of pins connected per logic block. It is shown that as the number of connected pins per block increases, the number of wiring tracks re- quired to route those blocks also increases. Since adding functionality to a block will lead to an increase in the number of connected pins, it follows that an increase in functionality of the block is only beneficial if the total number of blocks is reduced to more than compensate for the increased wiring area. This notion leads to the conclusion that the most area-efficient logic blocks are those with a high amount of functionality per pin.

关键词： logic arrays Field programmable gate arrays logic programming logic circuits Design automation programmable logic arrays logic gates Digital circuits Computer industry Industrial relations

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High-speed, cascaded optical logic operations using programmable optical logic gate arrays

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IEEE PHOTONICS TECHNOLOGY LETTERS 1996年第1期8卷 166-168页

作者： Lu, B Lu, YC Cheng, J Hafich, MJ Klem, J Zolper, JC SANDIA NATL LABS ALBUQUERQUENM 87185

programmable optical logic operations are demonstrated using arrays of nonlatching binary optical switches consisting of vertical-cavity surface emitting lasers, p-i-n photodetectors and heterojunction bipolar transistors. Individual arrays can perform Boolean optical logic functions at 100 Mb/s using both optical and electrical logic inputs, while the routing and fan-out of the optical logic outputs can be controlled at the gate level. Cascaded optical logic operation is demonstrated using two programmable logic gate arrays.

关键词： High speed optical techniques Optical arrays programmable logic arrays logic gates logic arrays Vertical cavity surface emitting lasers Optical switches Quantum cascade lasers Surface emitting lasers PIN photodiodes

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logic SYNTHESIS FOR FIELD-programmable GATE arrays

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1994年第10期13卷 1280-1287页

作者： HWANG, TT OWENS, RM IRWIN, MJ WANG, KH PENN STATE UNIV DEPT COMP SCIUNIVERSITY PKPA 16802 NATL CHIAO TUNG UNIV DEPT COMP SCI & INFORMAT ENGNHSINCHU 30043TAIWAN

In this paper, we consider the problem of configuring Field programmable Gate arrays (FPGA's) so that some given function is computed by the device. Obtaining the information necessary to configure a FPGA entails both logic synthesis and logic embedding. Due to the very constrained nature of the embedding process, this problem differs from traditional multilevel logic synthesis in that the structure (or lack thereof) of the synthesized logic is much more important. Furthermore, a metric-like literal count is much less important. We present a communication complexity-based decomposition technique that appears to be more suitable for FPGA synthesis than other multilevel logic synthesis methods. The key is that our logic optimization technique based on reducing communication complexity is good enough to allow a simple technology mapping to work well for FPGA devices.

关键词： logic arrays Field programmable gate arrays logic devices Circuit synthesis Table lookup programmable logic arrays Integrated circuit interconnections Very large scale integration Computer science Complexity theory

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