programmable logic controllers (PLCs) have been of great eminence in manufacturing systems and will probably remain predominant for some time to come. To allow re-implementation on a new hardware and visualization of ...
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ISBN:
(纸本)0780395670
programmable logic controllers (PLCs) have been of great eminence in manufacturing systems and will probably remain predominant for some time to come. To allow re-implementation on a new hardware and visualization of existing code, a formalization approach for PLC programs is proposed. The method presented here is not restricted to binary operations in the PLC code but also considers digital operations. In order to achieve compact visualization and efficient re-implementation an abstraction of the low level Instruction List (IL) programs is developed. The formalization of the abstracted code results in a compact finite state machine representation. The method is implemented using JAVA and XML technologies. The IL is converted to XML, the XML document object model (DOM) is used for parsing and scalable vector graphics (SVG) is employed to graphically represent the resulting automata. The presented approach is illustrated using STEP 5 IL from Siemens. The method is however generic, other IL dialects could be parsed if the corresponding description files are built.
Time has become a major obstacle in safety-critical systems. Although model checkers have gained application in the verification of timed control models, the actual implementation of these models is seldom verified. C...
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ISBN:
(纸本)9789806560543
Time has become a major obstacle in safety-critical systems. Although model checkers have gained application in the verification of timed control models, the actual implementation of these models is seldom verified. Common realtime models like timed automata assume perfect clocks and instantaneous reaction, which is not true for real systems. For timed systems this leads to the problem that not only the control program but also the controller and the environment affect the systems semantics. An implementation that is correct on perfect hardware can become void on real hardware due to its changed semantics. When a timed automaton model is to be implemented on a programmablelogic controller, the models semantics should match the controllers semantics. The adaption of the models semantics affects the enumeration of its reachable states.
This paper describes a programmable time measurement architecture that facilitates memory characterization. We have created a novel standalone time measurement architecture that can measure rise time, fall time, pulse...
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ISBN:
(纸本)0769523412
This paper describes a programmable time measurement architecture that facilitates memory characterization. We have created a novel standalone time measurement architecture that can measure rise time, fall time, pulse width and propagation delay time measurements without the need of additional circuitry [1] or circuit duplication [2]. This is achieved by the use of Time-to-Digital Conversion (TDC) based on the dual-slope principle. The key feature of the proposed architecture is programmability through the use of a novel programmable input stage. Furthermore, a current steering Time-to-Voltage Converter (TVC) is used in order to improve the linearity and dynamic range as compared to recent designs. The proposed architecture has been designed using 0.18 mu m CMOS process and results from simulations using foundry models suggest it is possible to achieve a timing resolution of 103ps. The measurement core size is 110 mu m x 75 mu m.
Recently companies focus on traceability in the factory to control the risk to the products. It is an important task to collect many IDs marked on the items and sections to realize traceability;much equipment for IDs ...
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ISBN:
(纸本)9780780394018
Recently companies focus on traceability in the factory to control the risk to the products. It is an important task to collect many IDs marked on the items and sections to realize traceability;much equipment for IDs collection is required in the factory. This paper discusses the application to traceability of the information-connection unit of the programmablelogic Controller (PLC). This unit has a script engine, and the capability to communicate with information systems without a computer for enterprise application integration (EAI). Therefore, the data held by the PLC is integrated with such information systems as Manufacturing Execution System (MES), at less cost, less time, and easier. It is shown that this unit is also useful for traceability, which is regarded as one of its main functions.
An accurate power line cable model is presented along with a higher level companion model which separates common-mode and pair mode-propagation in realistic residential power line network topologies. We describe physi...
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ISBN:
(纸本)0780388674
An accurate power line cable model is presented along with a higher level companion model which separates common-mode and pair mode-propagation in realistic residential power line network topologies. We describe physical models for common 14/2-10/2 and 14/3-8/3 cables with ground that include all propagating modes: differential-mode(s), pair-mode, and common-mode to "earth". The basic cable model is suitable for computing channel response and common mode currents in simple topologies using matrix or SPICE circuit simulation. The higher level companion model incorporates ground bonding at the service panel and readily facilitates analysis of complex network topologies using transmission-matrix methods. Signal flow methods are demonstrated for parameter extraction and assessing dominant paths relevant to both channel characterization and electromagnetic compatibility.
Transformers with magnetic core are commonly used in PLC systems for both capacitive style and inductive style couplers. The choice of the magnetic material for such cores greatly influences the geometric dimensions a...
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ISBN:
(纸本)0780388445
Transformers with magnetic core are commonly used in PLC systems for both capacitive style and inductive style couplers. The choice of the magnetic material for such cores greatly influences the geometric dimensions and the ultimate performance of the inductive components used in PLC couplers. VITROPERM, with its high saturation flux density and high permeability, is a very good choice of core material for such coupler applications.
The developer of logic control systems is faced with increasing complexity of the functions to be implemented and, at the same time, increasing demands on the reliability of the resulting software: To analyze the reli...
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ISBN:
(纸本)078039402X
The developer of logic control systems is faced with increasing complexity of the functions to be implemented and, at the same time, increasing demands on the reliability of the resulting software: To analyze the reliability of such complex systems formal methods can be applied. One area of the corresponding research is focused on the application of model checking techniques to programmable logic controllers (PLCs). In this paper a new method to formalize PLC programs together with a model of the cyclic behavior of the PLC is presented. The control systems behavior is modeled, and then the program, written in Instruction List, is formalized and integrated into the model. The formalization in SMV language is suitable for verification using BDD and SAT techniques. Both techniques are compared using first results of a case study.
We propose a cryptographic accelerator for IPsec by using the NEC electronics' Dynamically Reconfigurable Processor (DRP). In our system, an embedded processor and DRP are integrated in a System-on-a-Chip (SoC) an...
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ISBN:
(纸本)0780394070
We propose a cryptographic accelerator for IPsec by using the NEC electronics' Dynamically Reconfigurable Processor (DRP). In our system, an embedded processor and DRP are integrated in a System-on-a-Chip (SoC) and multiple cryptographic tasks can be accelerated by DRP Moreover, the virtual hardware mechanism, which dynamically changes its configuration data set, is introduced to realize more tasks on DRP The evaluation results show that the through-put of each implemented cryptographic task outperformed a MIPS compatible embedded processor from 1.6 times to 7.8 times. In addition, it is shown that 80.7% of the run-time configuration overhead can be reduced by background configuration based on the double buffering method.
This paper analyses the use of two control software design methodologies for developing a solution to control an automated manufacturing cell. Two separate approaches, Sequential Function Charts and an object-modellin...
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ISBN:
(纸本)0780390989
This paper analyses the use of two control software design methodologies for developing a solution to control an automated manufacturing cell. Two separate approaches, Sequential Function Charts and an object-modelling tool called Enterprise Controls are compared and contrasted with a view to establishing the effectiveness of each approach. These experiences are illustrated by comparing software to operate a simple clamp. Enterprise Controls provided a simpler solution, which reduced both the time taken for implementation of process changes as well as the need for these to be carried out by trained personnel. The experience showed that the object modelling approach provides benefits to manufacturers by aiding manufacturing flexibility, though this comes with a processor overhead. Concerns remain as to whether or not Enterprise Controls will be accepted by practicing control engineers in industry. Further work to quantify these benefits is planned.
As technology sizes decrease and die area increases, designers are creating increasingly complex computing systems using FPGAs. TO reduce design time for new products, the reuse of previously designed Intellectual Pro...
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ISBN:
(纸本)0769524451
As technology sizes decrease and die area increases, designers are creating increasingly complex computing systems using FPGAs. TO reduce design time for new products, the reuse of previously designed Intellectual Property (IP) cores is essential. However, since no universally accepted interface standards exist for IP cores, there is often a certain amount of redesign necessary before they are incorporated into the new system. Furthermore, the core's functionality may need updating to support the requirements of the new application. This paper demonstrates how the SIMPPL system model allows designers to rapidly implement on-chip systems comprising multiple Computing Elements (CEs). Furthermore, using a controller-based interface to manage inter-CE transfers enables users to easily adapt the control sequence of individual CEs to suit the needs of new applications without necessitating the redesign of other elements in the system. Two systems using three different hardware modules adapted to CEs are described to illustrate the power and simplicity of the SIMPPL model. It required a total of six hours to implement both designs on-chip once the individual CEs had been designed.
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