In the paper the state assignment methods of the finite state machines for PAL-based structures are presented. A main feature of the PAL-cell is a limited number of product terms (k-AND-gates) that are connected to a ...
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ISBN:
(纸本)0769524338
In the paper the state assignment methods of the finite state machines for PAL-based structures are presented. A main feature of the PAL-cell is a limited number of product terms (k-AND-gates) that are connected to a single sum (OR-gate). Function, which is the sum of p-implicants, when p not equal k, does not take full advantage of the cell. When p > k, implementation is multi-cell (so multi-level). The main idea of solving this problem is to count the number of product terms during the process of state assignment. First algorithm leads to automata which take advantage of the number of PAL-cell terms. Second approach is dedicated to state assignment of fast automata. Methods based on Primary and Secondary Merging Conditions are presented. In one of the most basic states of the logic synthesis of sequential devices, the elements referring to restrictions of PAL-based CPLDs are taken into account.
The MatPLC is an international project to develop a program similar to a PLC (programmablelogic Controller) for POSIX operating systems. It is an open source application consisting of a core, generic modules, and too...
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ISBN:
(纸本)9780780394018
The MatPLC is an international project to develop a program similar to a PLC (programmablelogic Controller) for POSIX operating systems. It is an open source application consisting of a core, generic modules, and tools for creating custom modules. Since many control and monitoring systems are distributed in nature, they require that the application be running on an embedded system capable of withstanding harsh environments. This paper describes the porting of the MatPLC code base to a commercial embedded system running on a PowerPC CPU. Time measurements were taken to determine whether the resulting code would be suitable for control applications.
An adaptive Mamdani based fuzzy logic controller has been designed for controlling a Static Compensator (STATCOM) in a multimachine power system. Such a controller does not need any prior knowledge of the plant to be ...
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We presents a novel design for a low dropout (LDO) voltage regulator is presented using floating-gate techniques to set the regulator output voltage and the ac and dc operating points of the circuit. In comparison wit...
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ISBN:
(纸本)0769524036
We presents a novel design for a low dropout (LDO) voltage regulator is presented using floating-gate techniques to set the regulator output voltage and the ac and dc operating points of the circuit. In comparison with conventional topologies, this approach does not require a feedback resistive divider or a bandgap reference to generate a temperature independent voltage. The use of floating-gates allows the regulator output to be programmed to a desired mode of operation and then stored in a non-volatile manner Experimental results are presented from a prototype circuit fabricated in MOSIS;this circuit has been functional in 2.0 mu m, 1.2 mu m, and 0.5 mu m processes available through MOSIS.
This paper describes an improved approach to design a Takagi-Sugeno zero-order type fast parameterized digital fuzzy logic controller (DFLC) processing only the active rules (rules that give a non-null contribution fo...
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ISBN:
(纸本)078039402X
This paper describes an improved approach to design a Takagi-Sugeno zero-order type fast parameterized digital fuzzy logic controller (DFLC) processing only the active rules (rules that give a non-null contribution for a given input data set), at high frequency of operation, without significant increase in hardware complexity. To achieve this goal, an improved method of designing the fuzzy controller model is proposed that significantly reduces the tame required to process the active rules and effectively increases the input data processing rate. The DFLC discussed in this paper achieves an internal core processing speed of at least 200 MHz, featuring two 8-bit inputs and one 12-bit output, with up to seven trapezoidal shape membership functions per input and a rule base of up to 49 rules. The proposed architecture was implemented in a Field programmable Gate Array (FPGA) chip with the use of a very high-speed integrated-circuits hardware-description-language (VHDL) and advanced synthesis and place and route tools.
This paper proposes a design for a fully programmable bus/memory controller. It enumerates the various advantages of such a controller, and demonstrates how modern memory models, common processor applications, and evo...
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ISBN:
(纸本)1595930590
This paper proposes a design for a fully programmable bus/memory controller. It enumerates the various advantages of such a controller, and demonstrates how modern memory models, common processor applications, and evolving operating system utilities point towards the use of the programmable controller as the next step forward in computer architecture. It also aims to evaluate the concerns that such a controller must take. Finally, It addresses a number of possible applications of a programmable controller, giving qualitative and quantitative analysis and sample implementations of several applications. Copyright 2005 ACM.
Sequential Function Chart (SFC) is a graphical programming language defined in IEC 61131-3 as a standard programming language for Programable logiccontrollers (PLCs). It provides an excellent method for formal specif...
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ISBN:
(纸本)0889865027
Sequential Function Chart (SFC) is a graphical programming language defined in IEC 61131-3 as a standard programming language for Programable logiccontrollers (PLCs). It provides an excellent method for formal specification of discrete events systems. In this paper we describe a method to implement SFCs using Field programmable Gate Arrays (FPGAs). The method is based on converting the SFC to a Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) which is a standard language used to configure FPGAs. The algorithm is successfully employed on an experimental platform using Xilinx Spartan-3 FPGA. Implementing SFCs on FPGAs satisfy the requirements of downsizing, hiding information, reducing costs, while adding high speed capabilities.
In this paper, the branched-bus topology is evaluated as representative of indoor PLC channels' multipath fading properties. The path amplitude and arrival-time distributions are investigated, as well as ranging o...
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Transmitton Ltd. is a competitive manufacturer of industrial control equipment in the UK. The company has embarked on a process of re-designing its products, using Hardware Description Languages (HDLs) and targeting r...
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The traffic light/voice controller is a sequential machine to be analyzed and programmed through a multistep process. Both the hands-on and the virtual environments are described. The design projects of the four teams...
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