An overview is given on the various aspects of formal approaches in logic control. First, the possibilities of combining several methods are discussed. Following this, the problems encountered by bringing the methods ...
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ISBN:
(纸本)0780372980
An overview is given on the various aspects of formal approaches in logic control. First, the possibilities of combining several methods are discussed. Following this, the problems encountered by bringing the methods into industrial applications are highlighted. Finally, common problems encountered in applying formal methods to PLC programming are identified.
In current industrial PLC programming there are a wide variety of logic control design methodologies in use. These languages include: ladder diagrams, function block diagrams, sequential function charts, and flow char...
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ISBN:
(纸本)0780372980
In current industrial PLC programming there are a wide variety of logic control design methodologies in use. These languages include: ladder diagrams, function block diagrams, sequential function charts, and flow charts. At the same time, driven by a desire for verifiability, academics are developing additional methodologies, such as modular finite state machines and Petri nets. Using these languages important properties of programs can be verified and some code can be generated automatically. However, in the development of recent programming languages almost no mention has been made of the human factor, which becomes important when an existing program is modified, debugged, or incorporated into a new program. To begin addressing this issue, we present three ways to measure the complexity of a logic program (time to develop, direct measurements, and accessibility measures) and measure similar programs written in three logic control design methodologies (ladder diagrams, Petri nets and modular finite state machines). The goal of this paper is not to provide definitive answers regarding the suitability of a language for a particular purpose, but rather to explore the factors that may affect such decisions in the future.
In this paper an interconnect IP (Intellectual Property) node architecture for flexible on-chip communication is introduced. This architecture is targeted for communication in future gigatransistor SoC (System-on-Chip...
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ISBN:
(纸本)0769514537
In this paper an interconnect IP (Intellectual Property) node architecture for flexible on-chip communication is introduced. This architecture is targeted for communication in future gigatransistor SoC (System-on-Chip) designs. The interconnect IP will be used as a testing platform when the efficiency of network topologies and routing schemes are investigated for on-chip environment. The interconnect node uses packet based communication and forms a reusable component itself. The node is constructed from a collection of parameterized and reusable hardware blocks. Those blocks include components such as FIFO buffers, routing controllers and standardized interface it-rappers. A node can be tuned to fulfill the desired characteristics of communication by selecting the internal architecture of the node properly. In the future the IP node forms a basic building component in SoC implementations.
We present a new resettable zero-knowledge proof system for graph 3-colorability with round complexity O(u(n) log(2) n), where u: N --> R>(0) is any unbounded function and n denotes the number of vertices in the...
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ISBN:
(纸本)3540002634
We present a new resettable zero-knowledge proof system for graph 3-colorability with round complexity O(u(n) log(2) n), where u: N --> R>(0) is any unbounded function and n denotes the number of vertices in the graph. Furthermore, we present a new formulation of the definition of resettable zero-knowledge and define and implement a knowledgeable commitment scheme: after the commitment phase the receiver is convinced that the sender knows a valid decommitment. This remains true even if the receiver is resettable, albeit with the drawback of non-constant round complexity. This is achieved by appending a resettable perfect witness-indistinguishable proof of knowledge of a decommitment to the original commit phase. We base all our constructions on a standard intractability assumption: the hardness of one of the many variants of the discrete logarithm problem.
This paper reports about the application of software engineering techniques to the analysis and design of logic and supervision control software for a complex manufacturing system, with particular regard to PLC-based ...
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ISBN:
(纸本)0780373863
This paper reports about the application of software engineering techniques to the analysis and design of logic and supervision control software for a complex manufacturing system, with particular regard to PLC-based control architectures. The design methodology presented in the paper rely on a mechatronic approach to the modularization of the whole problem, so that an efficient system decomposition can be performed, in order to reduce complexity of the softwaxe development task and increase flexibility and maintainability of the application. Modeling concepts derived from both Object-Oriented and Structured Analysis methods have been used to describe system modules and behaviour. However, some adaptations have been introduced, because the peculiarities of the manufacturing systems domain were difficult to express within an existing software design method. A practical case of study for the application of the design methodology proposed show that software engineering techniques can be applied successfully even in the unusual field of PLC-based control of manufacturing systems.
The paper presents the considerations relating to the Ways of analysis of ladder diagram created for small programmable controller (PLC) compact type which is equipped with simple keyboard for entry of such diagram. B...
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ISBN:
(纸本)0780374274
The paper presents the considerations relating to the Ways of analysis of ladder diagram created for small programmable controller (PLC) compact type which is equipped with simple keyboard for entry of such diagram. Because of the fact that compact PLC was built with using of, standard microcontroller which calculation power is small the authors met difficulties with translation, of the control program to the binary code. It was necessary to make decision that a ladder diagram will be not compiled but interpreted during program execution. The method of column by column analysis of ladder diagram was chosen as the most effective. The particular application of this method for small compact PLC,is presented in details-in the paper.
This poster presents the design of complex arbitration modules, like those required in SoC communication systems. Clock-less, delay-insensitive arbiters are studied in the perspective of making easier and more practic...
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ISBN:
(纸本)0769514715;0769514723
This poster presents the design of complex arbitration modules, like those required in SoC communication systems. Clock-less, delay-insensitive arbiters are studied in the perspective of making easier and more practical the design of future GALS or GALA SoCs. This work focuses on high-level modeling and delay-insensitive implementations of low-power and reliable fixed and dynamic priority arbiters.
The configuration of complex multi-part products often requires that a human expert be available to determine a compatible set of parts satisfying the specification. With the availability of on-line web catalogs, such...
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An architecture for one of the first mixed-signal field-programmable system-on-a-chip (FPSOC) is presented. The FPSOC integrates a 24-MHz 8-bit microcontroller, flash memory, SRAM, programmable analog and digital bloc...
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ISBN:
(纸本)0780372506
An architecture for one of the first mixed-signal field-programmable system-on-a-chip (FPSOC) is presented. The FPSOC integrates a 24-MHz 8-bit microcontroller, flash memory, SRAM, programmable analog and digital blocks, and on-chip clock generation. programmable interconnect has been designed to allow analog and digital blocks to be combined to form a wide variety of functional modules.
In a programmablelogic controller of a discrete-event control system, up to 60% of the coding effort is devoted to dealing with interlocking. Stage programming is a new concept by breaking a program into logical stag...
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In a programmablelogic controller of a discrete-event control system, up to 60% of the coding effort is devoted to dealing with interlocking. Stage programming is a new concept by breaking a program into logical stages, making complex systems design easier. The stages can then be programmed individually without concern for how they will affect the rest of the program. To become truly competitive for Artificial Intelligence semantic implementation in industry, this paper introduces a knowledge representation for the Petri net-based programmablelogic controller stage program. The symbolic logic uses a conceptual graph to translate the sensor-based stage Petri nets directly to the predicate calculus with While-Loop expressions. An example is used to illustrate the proposed concept and method.
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