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arXiv 2024年

作者： Deric, Aleksa Mitard, Kyle Tajik, Shahin Holcomb, Daniel Department of Electrical and Computer Engineering University of Massachusetts Amherst United States Department of Electrical and Computer Engineering Worcester Polytechnic Institute United States

Driven by a need for ever increasing chip performance and inclusion of innovative features, a growing number of semiconductor companies are opting for all-inclusive System-on-Chip (SoC) architectures. Although Moore's Law has been able to keep up with the demand for more complex logic, manufacturing large dies still poses a challenge. Increasingly the solution adopted to minimize the impact of silicon defects on manufacturing yield has been to split a design into multiple smaller dies called chiplets which are then brought together on a silicon interposer. Advanced 2.5D and 3D packaging techniques that enable this kind of integration also promise increased power efficiency and opportunities for heterogeneous integration. However, despite their advantages, chiplets are not without issues. Apart from manufacturing challenges that come with new packaging techniques, disaggregating a design into multiple logically and physically separate dies introduces new threats, including the possibility of tampering with and probing exposed data lines. In this paper we evaluate the exposure of chiplets to probing by applying laser contactless probing techniques to a chiplet-based AMD/Xilinx VU9P FPGA. First, we identify and map interposer wire drivers and show that probing them is easier compared to probing internal nodes. Lastly, we demonstrate that delay-based sensors, which can be used to protect against physical probes, are insufficient to protect against laser probing as the delay change due to laser probing is only 0.792ps even at 100% laser power. © 2024, CC BY-NC-SA.

关键词： programmable logic controllers

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Real-Time Implementation of Intelligent Modeling and Control Techniques on a PLC Platform

Real-Time Implementation of Intelligent Modeling and Control...

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2008 IEEE Industry Applications Society Annual Meeting (IAS 2008), vol.4

作者： Curtis Parrott Ganesh K. Venayagamoorthy Missouri University of Science and Technology Rolla MO US Real-Time Power and Intelligent Systems Laboratory Missouri University of Science and Technology Rolla MO USA

programmable logic controllers (PLCs) have been used for many decades for standard control in industrial and factory environments. Over the years, PLCs have become computational efficient and powerful, and a robust platform with applications beyond the standard control and factory automation. Due to the new advanced PLC's features and computational power, they are ideal platforms for exploring advanced modeling and control methods, including computational intelligence based techniques such as neural networks, particle swarm optimization (PSO) and many others. Some of these techniques require fast floating-point calculations that are now possible in real-time on the PLC. This paper focuses on the Allen-Bradley ControlLogix brand of PLCs, due to their high performance and extensive use in industry. The design and implementation of a neurocontroller consisting of two neural networks, one for modeling and the other for control, and the training of these neural networks with particle swarm optimization is presented in this paper on a single PLC. The neurocontroller in this study is a power system stabilizer (PSS) that is used for power system oscillation damping. The PLC is interfaced to a power system simulated on the real time digital simulator. Real time results are presented showing that the PLC is a suitable hardware platform for implementing advanced modeling and control techniques for industrial applications.

关键词： Computational intelligence Modeling Neurocontrol Particle swarm optimization programmable logic controllers Power system stabilizer

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Green Data Transmission in Power Line Communications

Green Data Transmission in Power Line Communications

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IEEE Global Communications Conference

作者： Hongjian Sun Arumugam Nallanathan Nan Zhao Cheng-Xiang Wang Department of Electronic Engineering King's College London School of Information and Communication Engineering Dalian University of Technology School of Engineering & Physical Sciences Heriot-Watt University

ISBN: (纸本)9781467309202

This paper presents a green data transmission approach to enhance the energy efficiency of power line communications (PLC) by jointly utilizing signal detection and resource allocation techniques. Due to the awareness of the interference as enabled by the signal detection function, the proposed PLC system can adaptively adjust the transmission parameters. Furthermore, given a power budget, a performance optimization algorithm is proposed that maximizes the energy efficiency of PLC by optimally choosing the signal detection duration and the transmit power. Simulation results show that the proposed system can not only mitigate the effects of interference, but also considerably improve the energy efficiency of PLC when compared with the existing PLC systems.

关键词： Green data transmission Power line communications Energy efficiency Energy detection carrier transmission on power lines Energy efficiency data transmission programmable logic controllers signal acquisition INTERFERENCE EFFECTS transmission parameter

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FX3U - Tomorrow's technology

Elektron

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Elektron 2006年第3期23卷 4-4页

Mitsubhishi company has developed a new PLC compact controller system called FX3U, which is a high performance compact PLC with upto 384 control points, and adds greater flexibility and increased performance to the system. Various features of the system include flexibility due to application-specific special function modules, integrated real-time clock, and internal PID controller with autotuning. The brand has remained one of constant quality, reliability, innovation, and versatility to remain ahead of others in the market. The company has sold six million units of the system in every country of the world in the last 25 years. Analog adapters include those for voltage/current input, voltage-current output, PT100 input and thermocouple input.

关键词： programmable logic controllers

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Narrowband OFDM Power Line Communication Challenges, Standardization, and Semiconductor's Role

Narrowband OFDM Power Line Communication Challenges, Standar...

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IEEE Global Communications Conference

作者： Donald Shaver David H. Su Daniel Popa Texas Instruments Incorporated Smart Grid BU National Institute of Standards and Technology Information Technology Laboratory Itron Incorporated

ISBN: (纸本)9781479913510

In this paper, we focus on narrowband (NB) OFDM PLC standards and associated implementations operating in frequency bands below 500 kHz. With the emergence of the Smart Grid Automated Meter Infrastructure (AMI), an international PLC standards gap was identified requiring new technology to serve market needs for higher bitrates and increased robustness [1]. This paper provides a brief history of PLC technology alternatives and the emergence of NB OFDM PLC solutions that fill this "standards gap". We discuss power line channel impairments (e.g., noise, impedance) that we have measured on power grids and in dwellings such as in high rise buildings [2]. These studies have influenced emerging international NB OFDM PLC standards [3][4] and existing NB OFDM PLC solutions[5][6]. An important topic beyond NB PLC standardization is defining how the new modems coexist with legacy PLC modems operating in the same frequency band. SGIP PAP-15 [6] has done considerable work coordinating PLC coexistence requirements with IEEE P1901.2, ITU-T G.990x standards development;and PRIME and G3-PLC Alliances. Semiconductor's role is then to provide a hardware and software platform to realize a robust communications solution that can be deployed around the world. So then another important topic addressed is computational complexity. We roughly estimate modem computations as a function of signal bandwidth. This analysis shows that NB OFDM PLC standards can be implemented in software using a simple microprocessor;and in addition the same hardware platform can be used to implement the various standards.

关键词： Power line communication OFDM Narrowband PLC IEEE P1901.2 ITU-T G.9901 - G.9904 G3-PLC PRIME Coexistence Computational complexity Software-defined modems carrier transmission on power lines Orthogonal frequency division multiplexing complexity classes programmable logic controllers Coexistence Smart grids Standardization Modems Frequency bands

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Estimation of voltage sag using transient stability analysis and automation of power factor correction using PLC in a petrochemical industry

Estimation of voltage sag using transient stability analysis...

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IET Chennai Fourth International Conference on Sustainable Energy and Intelligent Systems (SEISCON 2013)

作者： Keerthi Jayaraj EEE Department M.G University Kerala India

ISBN: (纸本)9781510804524

The power quality, mainly voltage sag performance and power factor of a distribution system have been evaluated. The analysis of voltage sag uses the Monte-Carlo procedure carried out in the Electrical Transient Analysis Program (ETAP) to construct the sag density table and to estimate the probable number of critical voltage sags per annum at a given node. These calculations have taken into account the entire system comprising the transmission, sub transmission and distribution subsystems. Also, the various improvement methods for sag performance have been suggested. To improve power factor, a scheme for automation of power factor correction using programmable logic Controller (PLC) based on actual installations has been developed. For automation, Boolean logic circuit has been developed and ladder diagram has been drawn. From the ladder diagram, program for the PLC has been written.

关键词： Voltage sag Power factor correction Power quality Monte-Carlo Method programmable logic Controller voltage sags Power factor correction programmable logic controllers Monte Carlo technique Power quality Automation Petrochemical industry ladder diagram Reactive power transient stability dispensing system

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Reconfigurable architecture for spatial sensing in wideband radio front-end

arXiv

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arXiv 2021年

作者： Gupta, M. Miss, Somya Sharma Joshi, H. Darak, S.J. ECE Department IIIT-Delhi 110020 India

The deployment of cellular spectrum in licensed, shared and unlicensed spectrum demands wideband sensing over non-contiguous sub-6 GHz spectrum. To improve the spectrum and energy efficiency, beamforming and massive multi-antenna systems are being explored which demand spatial sensing i.e. blind identification of vacant frequency bands and direction-of-arrival (DoA) of the occupied bands. We propose a reconfigurable architecture to perform spatial sensing of multi-band spectrum digitized via wideband radio front-end comprising of the sparse antenna array (SAA) and Sub-Nyquist Sampling (SNS). Proposed architecture comprises SAA pre-processing and algorithms to perform spatial sensing directly on SNS samples. The proposed architecture is realized on Zynq System on Chip (SoC), consisting of the ARM processor and FPGA, via hardware-software co-design (HSCD). Using the dynamic partial reconfiguration (DPR), on-the-fly switching between algorithms depending on the number of active signals in the sensed spectrum is enabled. The functionality, resource utilization, and execution time of the proposed architecture are analyzed for various HSCD configurations, word-length, number of digitized samples, signal-to-noise ratio (SNR), and antenna array (sparse/non-sparse). Copyright © 2021, The Authors. All rights reserved.

关键词： programmable logic controllers

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Automated Formal Verification of a Highly-Configurable Register Generator

arXiv

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arXiv 2024年

作者： Zhang, Shuhang Olmos, Bryan Naik, Basavaraj Infineon Technologies AG Neubiberg Germany

Registers in IP blocks of an SoC perform a variety of functions, most of which are essential to the SoC operation. The complexity of register implementation is relatively low when compared with other design blocks. However, the extensive number of registers, combined with the various potential functions they can perform, necessitates considerable effort during implementation, especially when using a manual approach. Therefore, an in-house register generator was proposed by the design team to reduce the manual effort in the register implementation. This in-house register generator supports not only the generation of register blocks but also bus-related blocks. Meanwhile, to support various requirements, 41 generation options are used for this generator, which is highly-configurable. From the verification perspective, it is infeasible to achieve complete verification results with a manual approach for all options combinations. Besides the complexity caused by configurability, the register verification is still time-consuming due to two widely recognized issues: the unreliability of specifications and the complexity arising from diverse access policies. To deal with the highly-configurable feature and both register verification issues, we propose an automated register verification framework using formal methods following the Model Driven Architecture (MDA). Based on our results, the human effort in the register verification can be reduced significantly, from 20Person-Day (20PD) to 3PD for each configuration, and 100% code coverage can be achieved. During the project execution, eleven new design bugs were found with the proposed verification framework. Copyright © 2024, The Authors. All rights reserved.

关键词： programmable logic controllers

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Outage Probability Analysis of PLC with Channel Gain under Nakagami-m Additive Noise

Outage Probability Analysis of PLC with Channel Gain under N...

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IEEE Vehicular Technology Conference

作者： Aashish Mathur Manav R. Bhatnagar Bijaya K. Panigrahi Department of Electrical Engineering Indian Institute of Technology - Delhi Hauz Khas New Delhi 110016 India

ISBN: (纸本)9781479980925

Power line communication (PLC) deals with the transmission of data through the use of power lines. It is an emerging field of communication for the home area network of smart grid. The presence of the additive and multiplicative power line noises significantly affects the performance of PLC systems. There are two types of additive noises in PLC systems, namely background noise and impulsive noise. The multiplicative PLC noise results in fading in the received signal strength. The Rician fading model has been experimentally found to be applicable to the PLC systems and has been widely used in conventional and current literature on PLC. In this paper, we provide the performance analysis of a PLC system over Rician fading channel under Nakagami-m distributed additive background noise assuming binary phase shift keying modulation scheme. We derive the probability density function of the decision variable and the instantaneous signal-to-noise ratio (SNR). A closed-form expression of the outage probability of the considered system is obtained. The validity of the derived analytical expressions is closely verified by the simulated results.

关键词： Background noise binary phase shift keying Nakagami-m distribution outage probability power line communications Rician fading BACKGROUND NOISE Binary phase shift keying programmable logic controllers carrier transmission on power lines Rician fading Additive noise Probabilistic analysis Power cables

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MCU-Wide Timing Side Channels and Their Detection

arXiv

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arXiv 2023年

作者： Müller, Johannes Antón, Anna Lena Duque Deutschmann, Lucas Mehmedagić, Dino Rodrigues, Cristiano Oliveira, Daniel Devarajegowda, Keerthikumara Fadiheh, Mohammad Rahmani Pinto, Sandro Stoffel, Dominik Kunz, Wolfgang RPTU Kaiserslautern-Landau Germany Universidade do Minho Portugal Siemens EDA Germany Stanford University United States

Microarchitectural timing side channels have been thoroughly investigated as a security threat in hardware designs featuring shared buffers (e.g., caches) and/or parallelism between attacker and victim task execution. However, contradicting common intuitions, recent activities demonstrate that this threat is real even in microcontroller SoCs without such features. In this paper, we describe SoC-wide timing side channels previously neglected by security analysis and present a new formal method to close this gap. In a case study on the RISC-V Pulpissimo SoC, our method detected a vulnerability to a previously unknown attack variant that allows an attacker to obtain information about a victim’s memory access behavior. After implementing a conservative fix, we were able to verify that the SoC is now secure w.r.t. the considered class of timing side channels. Copyright © 2023, The Authors. All rights reserved.

关键词： programmable logic controllers

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