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A Technique for Bytecode Decompilation of PLC Program

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A Technique for Bytecode Decompilation of PLC Program

2017 IEEE 第2届先进信息技术,电子与自动化控制国际会议(IAEAC 2017)

作者： Xuefeng LV Yaobin Xie Xiaodong Zhu Lu Ren State Key Laboratory of Mathematical Engineering and Advanced Computing

Program logical controllers(PLCs) are the kernel equipment of industrial control system(ICS) as they directly monitor and control industrial processes. Recently, ICS is suffering from various cyber th

ISBN: (纸本)9781467389808

关键词： programmable logical controller Bytecode Decompilation Mapping rules address byte decompilation programmable logic controllers Integrated circuits

programmable logic arrays

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arXiv 2019年

作者： Damaj, Issam W. Dhofar University

This is the peer reviewed version of the following article: [I. Damaj, programmable logic Arrays, in Wiley Encyclopedia of Computer Science and Engineering, Benjamin Wah (Editor), Hoboken: John Wiley & Sons, Inc, New Jersey, January 15, 2008. V 4 P 2272 – 2280.], which has been published in final form at [https://***/10.1002/***316]. This article may be used for non-commercial purposes in accordance with Wiley Terms and Conditions for Use of Self-Archived Versions. Copyright © 2019, The Authors. All rights reserved.

关键词： programmable logic controllers

New PLC technologies improve information flow

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Assembly

Assembly 2006年第4期49卷 8-8页

The importance of programmable logic controllers (PLCs) in improving the information flow is discussed. PLCs have become smaller, cheaper and easier to use and can now provide motion control, interface with vision systems, and link to enterprise networks. PLCs are also called programmable automation controllers (PACs), that provide fully configurable I/O, motion control, human-machine interface (HMI) support, and direct device-to-enterprise connectivity. Engineers can monitor, control and program the PAC via Internet browsers and enterprise servers and the device can be controlled for various applications through six internal module bays. Besides this, the devices are also managing the assembly line.

关键词： programmable logic controllers

Non-parametric Mitigation of Periodic Impulsive Noise in Narrowband Powerline Communications

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Non-parametric Mitigation of Periodic Impulsive Noise in Nar...

IEEE Global Communications Conference

作者： Jing Lin Brian L. Evans Wireless Networking and Communications Group The University of Texas at Austin

ISBN: (纸本)9781479913510

Periodic impulsive noise synchronous to the main powerline frequency is the dominant noise component in OFDM-based narrowband (NB) powerline communications (PLC). Such noise occurs in periodic bursts, where a single burst could corrupt multiple OFDM symbols. Standardized NB PLC systems use frequency-domain interleaving (FDI) in combination with forward error correction to combat impulsive noise. Alternate designs adopt time-domain block interleaving (TDI) in which the receiver deinterleaver scatters an impulsive noise burst into short impulses over a large number OFDM symbols. In bursty impulsive noise, TDI-OFDM (FDI-OFDM) works better at high (low) SNR. In this paper, we develop non-parametric methods for periodic impulsive noise mitigation in coded TDI-OFDM systems. We exploit the sparse structure of the time-domain noise after the deinterleaver, and propose sparse Bayesian learning based algorithms that estimate and remove the noise impulses by observing the null and pilot tones of received signal and using decision feedback from the decoder. The proposed methods do not assume any statistical noise model and hence do not require any training. In simulations, the proposed methods in TDI-OFDM systems achieve up to 6 dB SNR gain over FDI-OFDM systems at typical NB PLC SNR values.

关键词： Impulse noise Power cables decision feedback Bayesian learning Forward error correction Noise models Periodic Narrowband programmable logic controllers received signal

Reflection principles, propositional proof systems, and theories

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arXiv 2020年

作者： Pudlák, Pavel

The reflection principle is the statement that if a sentence is provable then it is true. Reflection principles have been studied for first-order theories, but they also play an important role in propositional proof complexity. In this paper we will revisit some results about the reflection principles for propositional proofs systems using a finer scale of reflection principles. We will use the result that proving lower bounds on Resolution proofs is hard in Resolution. This appeared first in the recent article of Atserias and Müller [2] as a key lemma and was generalized and simplified in some spinoff papers [11, 13, 12]. We will also survey some results about arithmetical theories and proof systems associated with them. We will show a connection between a conjecture about proof complexity of finite consistency statements and a statement about proof systems associated with a *** Codes 03F20 Copyright © 2020, The Authors. All rights reserved.

关键词： programmable logic controllers

Arnold: an eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End-Nodes

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arXiv 2020年

作者： Schiavone, Pasquale Davide Rossi, Davide Mauro, Alfio Di Gürkaynak, Frank Saxe, Timothy Wang, Mao Yap, Ket Chong Benini, Luca Integrated Systems Laboratory D-ITET ETH Zürich Zürich8092 Switzerland Energy-Efficient Embedded Systems Laboratory DEI University of Bologna Bologna40126 Italy QuickLogic Corporation 2220 Lundy Ave San JoseCA95131 United States

A wide range of Internet of Things (IoT) applications require powerful, energy-efficient and flexible end-nodes to acquire data from multiple sources, process and distill the sensed data through near-sensor data analytics algorithms, and transmit it wirelessly. This work presents Arnold: a 0.5 V to 0.8 V, 46.83 µW/MHz, 600 MOPS fully programmable RISC-V Microcontroller unit (MCU) fabricated in 22 nm Globalfoundries GF22FDX (GF22FDX) technology, coupled with a state-of-the-art (SoA) microcontroller to an embedded Field programmable Gate Array (FPGA). We demonstrate the flexibility of the System-On-Chip (SoC) to tackle the challenges of many emerging IoT applications, such as (i) interfacing sensors and accelerators with non-standard interfaces, (ii) performing on-the-fly pre-processing tasks on data streamed from peripherals, and (iii) accelerating near-sensor analytics, encryption, and machine learning tasks. A unique feature of the proposed SoC is the exploitation of body-biasing to reduce leakage power of the embedded FPGA (eFPGA) fabric by up to 18× at 0.5 V, achieving SoA state bitstream-retentive sleep power for the eFPGA fabric, as low as 20.5 µW. The proposed SoC provides 3.4× better performance and 2.9× better energy efficiency than other fabricated heterogeneous re-configurable SoCs of the same class. Copyright © 2020, The Authors. All rights reserved.

关键词： programmable logic controllers

PIM-AI: A NOVEL ARCHITECTURE FOR HIGH-EFFICIENCY LLM INFERENCE

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arXiv 2024年

作者： Ortega, Cristobal Falevoz, Yann Ayrignac, Renaud UPMEM Grenoble France

Large Language Models (LLMs) have become essential in a variety of applications due to their advanced language understanding and generation capabilities. However, their computational and memory requirements pose significant challenges to traditional hardware architectures. Processing-in-Memory (PIM), which integrates computational units directly into memory chips, offers several advantages for LLM inference, including reduced data transfer bottlenecks and improved power efficiency. This paper introduces PIM-AI, a novel DDR5/LPDDR5 PIM architecture designed for LLM inference without modifying the memory controller or DDR/LPDDR memory PHY. We have developed a simulator to evaluate the performance of PIM-AI in various scenarios and demonstrate its significant advantages over conventional architectures. In cloud-based scenarios, PIM-AI reduces the 3-year TCO per queries-per-second by up to 6.94x compared to state-of-the-art GPUs, depending on the LLM model used. In mobile scenarios, PIM-AI achieves a 10- to 20-fold reduction in energy per token compared to state-of-the-art mobile SoCs, resulting in 25 to 45 % more queries per second and 6.9x to 13.4x less energy per query, extending battery life and enabling more inferences per charge. These results highlight PIM-AI's potential to revolutionize LLM deployments, making them more efficient, scalable, and sustainable. Copyright © 2024, The Authors. All rights reserved.

关键词： programmable logic controllers

Real-time detection and adaptive mitigation of power-based side-channel leakage in SoC

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arXiv 2021年

作者： Kiaei, Pantea Yao, Yuan Schaumont, Patrick Worcester Polytechnic Institute WorcesterMA01609 United States Virginia Tech BlacksburgVA24061 United States

Power-based side-channel is a serious security threat to the System on Chip (SoC). The secret information is leaked from the power profile of the system while a cryptographic algorithm is running. The mitigation requires efforts from both the software level and hardware level. Currently, there is no comprehensive solution that can guarantee the whole complex system is free of leakage and can generically protect all cryptographic algorithms. In this paper, we propose a real-time leakage detection and mitigation system which enables the system to monitor the side-channel leakage effects of the hardware. Our proposed system has extensions that provide a real-time monitor of power consumption, detection of side-channel leakage, and real-time adaptive mitigation of detected side-channel leakage. Our proposed system is generic and can protect any algorithm running on it. © 2021, CC BY.

关键词： programmable logic controllers

Gemmini: Enabling systematic deep-learning architecture evaluation via full-stack integration

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arXiv 2019年

作者： Genc, Hasan Kim, Seah Amid, Alon Haj-Ali, Ameer Iyer, Vighnesh Prakash, Pranav Zhao, Jerry Grubb, Daniel Liew, Harrison Mao, Howard Ou, Albert Schmidt, Colin Steffl, Samuel Wright, John Stoica, Ion Ragan-Kelley, Jonathan Asanovic, Krste Nikolic, Borivoje Shao, Yakun Sophia UC Berkeley MIT

DNN accelerators are often developed and evaluated in isolation without considering the cross-stack, system-level effects in real-world environments. This makes it difficult to appreciate the impact of System-on-Chip (SoC) resource contention, OS overheads, and programming-stack inefficiencies on overall performance/energy-efficiency. To address this challenge, we present Gemmini, an open-source1, full-stack DNN accelerator generator. Gemmini generates a wide design-space of efficient ASIC accelerators from a flexible architectural template, together with flexible programming stacks and full SoCs with shared resources that capture system-level effects. Gemmini-generated accelerators have also been fabricated, delivering up to three orders-of-magnitude speedups over high-performance CPUs on various DNN benchmarks. Copyright © 2019, The Authors. All rights reserved.

关键词： programmable logic controllers