Cobham Gaisler develops the LEON3FT SPARC V8 fault-tolerant microprocessor that is available both as IP cores part of an IP library (GRLIB) that allows users to design their own custom system-on-chip (SoC) designs, an...
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ISBN:
(纸本)9789292212964
Cobham Gaisler develops the LEON3FT SPARC V8 fault-tolerant microprocessor that is available both as IP cores part of an IP library (GRLIB) that allows users to design their own custom system-on-chip (SoC) designs, and also as part of ready-made designs and devices. Cobham Gaisler has recently added support for Microsemi IGLOO2, and experimental support for Microsemi radiation-tolerant RTG4, devices to GRLIB.
Field programmable gate arrays (FPGAs) are fundamental flexible integrated circuits that enable engineers to program any circuits that they want in the field. If we want to mention a practical building block of a syst...
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In the current market context, industries need to constantly remain technically competitive. Such context in which customers require personalized products force them to design better products at shorter development cy...
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作者：
Riera, B.Philippot, A.Coupat, R.Gellot, F.Annebicque, D.
Moulin de la Housse BP 1039 Reims51687 France
Direction de l'Ingénierie Société Nationale des Chemins de Fer Français 6 avenue François Mitterrand La-Plaine-Saint Denis Cedex93574 France
IUT de Troyes 9 rue de Québec BP 396 Troyes Cedex10026 France
This paper presents an original non-intrusive method to make safe existing programmablelogic Controller (PLC) program for manufacturing systems. In this work, manufacturing systems are considered as Discrete Event Sy...
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The Common Industrial Protocol (CIP) is a widely used Open DeviceNet Vendors Association (ODVA) standard [14]. CIP is an application-level protocol for communication between components in an industrial control setting...
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A critical step towards certifying safety-critical systems is to check their conformance to hard realtime requirements. A promising way to achieve this is by building the systems from pre-verified components and verif...
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The software of programmable logic controllers (PLC) for Safety Instrumented Systems in the oil and gas industry is designed based on safety specifications that must be validated prior to deployment. This paper propos...
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Connectors and connection technologies are perceived as a major innovation driver in digitalization and networking of future production facilities, as its interface functionality in between machines, programmable logi...
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Constrained Random Verification (CRV) is becoming the mainstream methodology for the functional verification of complex System on Chip (SoC) designs. In order to achieve verification closure, CRV tools have to produce...
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This study proposes an algorithm for generating the associated Boolean expression in VHDL, given a ladder diagram (LD) as the input. The purpose of the algorithm is to implement of field-programmable gate array-(FPGA-...
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This study proposes an algorithm for generating the associated Boolean expression in VHDL, given a ladder diagram (LD) as the input. The purpose of the algorithm is to implement of field-programmable gate array-(FPGA-) based programmable logic controllers (PLCs), where an effective conversion from an LD to its associated Boolean expressions seems rarely mentioned. Based on this core thought, the conversion process of the algorithm first involves abstracting and expressing the encountered LD as an activity-on-vertex (AOV) graph. Next, an AND-OR tree in which AND-nodes and OR-nodes connote the series and the parallel relationships between the vertices of the AOV graph is constructed based on the AOV graph. Therefore, by a traversal to the AND-OR tree, the associated Boolean expression, as the output of the algorithm, can be easily obtained in VHDL. The proposed algorithm is then verified with an illustrative example, wherein a complicated LD is given as the input.
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