Since their introduction in the 1970s, programmable logic devices (PLDs) evolved from implementing small glue-logic designs to large, configurable multi-processor Systems-on-Chip (SoC). Today's most prominent PLD ...
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Since their introduction in the 1970s, programmable logic devices (PLDs) evolved from implementing small glue-logic designs to large, configurable multi-processor Systems-on-Chip (SoC). Today's most prominent PLD technology, known as FPGA (Field-programmable Gate Array), is used in an increasing number of application domains, such as the telecom industry, the automotive electronics sector or automation technology, and recent market studies expect a continuous demand for these sophisticated microelectronic devices in the future. For small and medium enterprises and/or SME-dominated countries like Austria, FPGAs can provide access to VLSI (Very Large Scale Integration) technology by avoiding the immense NRE (Non-Recurring Engineering) costs of ASICs (Application-Specific Integrated Circuits). This work outlines how today's and future electronic-based systems can benefit from FPGA technology. Trends, tools and design flows will be explained as well as research challenges that are currently investigated within two public funded R&D projects at the University of Applied Sciences Technikum Wien.
The author describes an undergraduate computer engineering curriculum using a rapid prototyping approach to simulate, synthesize, and implement digital system and computer architectures.
The author describes an undergraduate computer engineering curriculum using a rapid prototyping approach to simulate, synthesize, and implement digital system and computer architectures.
The use of the combinational/register coordinate system as a graphical way of measuring programmable logic devices (PLDs) in terms of gates and registers is reviewed. It is assumed that the I/O resources of the PLD, w...
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The use of the combinational/register coordinate system as a graphical way of measuring programmable logic devices (PLDs) in terms of gates and registers is reviewed. It is assumed that the I/O resources of the PLD, which constitute a third axis, are adequate. This allows the analysis to be restricted to an x-y plane fixed along the z-axis. The device's application area, which is the area bounded by its combinational and register capability, is discussed, and methods for calculating the application range are described. Three brief examples demonstrate the ways in which the coordinate system might be used in CAD tools that automate the PLD design process.< >
A family of CMOS erasable programmable logic devices (EPLDs) is described with emphasis on the state-of-the-art chip architecture and circuit design techniques. The main features of this family of EPLDs include zero s...
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A family of CMOS erasable programmable logic devices (EPLDs) is described with emphasis on the state-of-the-art chip architecture and circuit design techniques. The main features of this family of EPLDs include zero standby power, high-speed operation, flip-flop reconfigurability, small chip size, and high reliability. A novel input-transition-detection circuit allows the chip to consume no power during standby and yet wakes the chip up with minimum delay. Basic architectural differences between EPLDs and EPROM are discussed that require extra design considerations to achieve an optimal speed path through the array. A direct-drive technique is used in the transistor-transistor logic buffer and flip-flop circuits to improve speed, layout area, and chip organization.
X-BLOX, a software tool for mapping architecture-independent designs to field-programmable gate arrays (FPGAs), is described. X-BLOX synthesizes a delay- and area-efficient logic-level design from an input specificati...
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X-BLOX, a software tool for mapping architecture-independent designs to field-programmable gate arrays (FPGAs), is described. X-BLOX synthesizes a delay- and area-efficient logic-level design from an input specification consisting of a network of generic modules. The tool automatically propagates partial data type specification, performs architecture-specific design optimization, and performs context-dependent module synthesis.
Focuses on customizing programmable logic devices by several manufacturers and its effect on application specific integrated circuits (ASIC). Changes considered by manufacturers in the development of logicdevices; Ov...
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Focuses on customizing programmable logic devices by several manufacturers and its effect on application specific integrated circuits (ASIC). Changes considered by manufacturers in the development of logicdevices; Overlapping of programmablelogic and ASIC users; Improvement in the performance of logicdevices. INSET: Software's role in next-generation..., by Roland L. Mattison.
The inclusion of modular functional units is often used as an example of how environmental considerations can be incorporated in the design stage of electronic products. The assumption is that the functional units can...
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ISBN:
(纸本)1424403510
The inclusion of modular functional units is often used as an example of how environmental considerations can be incorporated in the design stage of electronic products. The assumption is that the functional units can can be reused at end of life to perform the same task in a different product. The environmental benefit from this practice is only accrued if the feedback loop from recovery to remanufacture is completed. The barriers to the completion of this loop are numerous and concern compatability, reliability, functionality, flexibility and cost inter alia. This paper discusses the concept of modular digital electronic circuits based on programmablelogic device technology and examines their suitability for use in the scheme of an overall Eco-design methodology based on the re-use of such modular units. A comparative streamlined life cycle assessment between this methodology and conventional digital electronics is also conducted to inspect the environmental benefits across the whole life cycle.
This book is a monograph devoted to logic synthesis and optimization for CPLDs. CPLDs' macrocell can also be interpreted as programmable AND-fixed OR structure, well known as PAL-based structure. The question is: ...
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ISBN:
(数字)9783642361661
ISBN:
(纸本)9783642361654;9783642361661
This book is a monograph devoted to logic synthesis and optimization for CPLDs. CPLDs' macrocell can also be interpreted as programmable AND-fixed OR structure, well known as PAL-based structure. The question is: what should be done when the number of implicants representing function exceeds the number of product terms available in a logic block. The answer is ... in the book. logic synthesis and optimization methods dedicated for PAL-based structures are proposed. The methods strive to find the optimum fit for the combinational logic and finite state machines to the structure of the logic device and aim at area and speed optimization. The theoretical background and complete strategies are richly illustrated with examples and figures.
programmable logic devices (FPGAs) and (CPLDs) often use Flash memory as internal or external configuration memory for storing startup bit streams. Flash memory has the characteristic of non-volatility and can usually...
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ISBN:
(数字)9798350378412
ISBN:
(纸本)9798350378412
programmable logic devices (FPGAs) and (CPLDs) often use Flash memory as internal or external configuration memory for storing startup bit streams. Flash memory has the characteristic of non-volatility and can usually maintain data without loss for a long time. However, under extreme conditions such as high temperature, unstable working voltage, or radiation interference, Flash memory data retention may sharply decrease, which can affect the lifespan of Flash memory products and cause abnormal operation of programmable logic devices. Based on the Flash memory dual boot bitstream scheme, two bitstreams are backed up to each other, and a self-test module circuit is used. After the programmablelogic device is powered on and loaded to complete startup, the self-test module circuit performs periodic self-test of the stored bitstreams in Flash memory. The correct bitstreams that are backed up to each other are used to correct errors in the bitstreams, protect the security of Flash memory data, avoid errors in Flash memory data, and thereby affect the safe programming and normal startup work of the programmablelogic device. The results of software simulation and board level testing verification show that the secure programming startup technology for programmable logic devices based on Flash memory dual boot bit streams can effectively and timely correct Flash memory error bit streams. At the same time, this technology can reduce the theoretical failure rate of Flash memory data from 0.7% (1-year failure rate and exponential increase over time) to 0.0049%, and this failure rate does not accumulate over time. This technology can enhance the security and reliability of Flash memory data, ensuring the safe programming and normal startup of programmable logic devices, which proves the feasibility and effectiveness of the research results of this technology.
This paper argues towards the usage of programmable logic devices as supporting platforms for experimentation, from introductory to advanced courses, including microprocessor-based system design, within a typical &quo...
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This paper argues towards the usage of programmable logic devices as supporting platforms for experimentation, from introductory to advanced courses, including microprocessor-based system design, within a typical "embedded systems track" course structure in the framework of a Electrical and Computer Engineering curriculum. We argue that the usage of programmable logic devices is adequate to be adopted as common implementation platform, whenever the design of digital and embedded systems should be introduced. A remote laboratory, taking advantage of dynamic reconfiguration of programmable logic devices, is proposed, giving adequate support for remote experimentation, and additional opportunities to the students to get involved with experimentation, on top of simulation environments already in use and physical experimentation in crowded laboratories.
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