When designing fault-tolerant systems including programmable logic arrays (PLAs), the various aspects of these circuits concerning fault diagnosis have to be taken into account. The peculiarity of these aspects, rangi...
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When designing fault-tolerant systems including programmable logic arrays (PLAs), the various aspects of these circuits concerning fault diagnosis have to be taken into account. The peculiarity of these aspects, ranging from fault models to test generation algorithms and to self-checking structures, is due to the regularity of PLAs. The fault model generally accepted for PLAs is the crosspoint defect; it is employed by dedicated test generation algorithms, based on the fact that PLAs implement a two-level combinational function. The problem of accessing inputs and outputs of the PLA can be alleviated by augmenting the PLA itself so as to simplify the test vectors to be applied, making them function independent in the limit. A further step consists in the addition of the circuitry required to generate test vectors and to evaluate the answer, thus obtaining a built-in self-test (BIST) architecture. Finally, high reliability can be achieved with PLAs featuring concurrent error detection.
We analyze the performance of various heuristic algorithms for minimizing realizations of multiple-valued functions by the newly developed CCD [9] and CMOS [15] programmable logic arrays. The functions realized by suc...
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We analyze the performance of various heuristic algorithms for minimizing realizations of multiple-valued functions by the newly developed CCD [9] and CMOS [15] programmable logic arrays. The functions realized by such PLA's are in sum-of-products form, where sum is ordinary addition truncated to the highest logic value, and where product represents the MIN operation on functions of the input variables which are the interval literal operations. We compare three previously published heuristics, Pomper and Armstrong [14], Besslich [3], and Dueck and Miller [6], over sets of random and random symmetric functions. We show an exact minimization method that is a tree search using backtracking. A considerable reduction in the search space is achieved by considering constrained implicant sets and by eliminating some implicants altogether. Even with this improvement, the time required for exact minimization is extremely high when compared to all three heuristics. We also examine the case where only prime implicants are considered and show that such implicants have marginal value compared to constrained implicant sets. Our basis of comparison is the average number of product terms. We show that the heuristic methods are reasonably close to minimal and produce nearly the same average number of product terms. Interestingly though, there is surprisingly little overlap in the set of functions where the best realization is achieved. Thus, there is a benefit to applying all three heuristics to a given function and then choosing the best realization.
Redundancy techniques have been applied to conventional programmable logic arrays (PLAs) to allow for the repair of defective chips. When the redundancy technique is implemented in a VLSI or WSI chip design, the incre...
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Redundancy techniques have been applied to conventional programmable logic arrays (PLAs) to allow for the repair of defective chips. When the redundancy technique is implemented in a VLSI or WSI chip design, the increased cost is proportional to the increased chip silicon area, and the additional spare lines can increase the silicon area and propagation delay. However, if the provided redundancy can be efficiently utilized to repair defective chip; then the additional spare lines may increase rather than decrease the chip yields. The possibility of yield enhancement through redundant design is analyzed, showing that the chip yield is increased significantly.< >
A testable design of programmable logic arrays (PLAs) with high fault coverage for random test patterns is introduced. Low area overhead is achieved by adding a mask array between the input-decoder and the AND array o...
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A testable design of programmable logic arrays (PLAs) with high fault coverage for random test patterns is introduced. Low area overhead is achieved by adding a mask array between the input-decoder and the AND array of the PLA. Several variations of the proposed approach are presented. The probability of fault detection and the test length are examined for both stuck-type and crosspoint-type faults to estimate the fault coverage achievable with the random patterns.< >
作者：
Hwang, GHShen, WZTelecommunication Laboratories
Model Shop VLSI Support Center Ministry of Transportation and Communications 12 Lane 551 Min-Tsu Road Sec. 3 Yang-Mei Taoyuan Taiwan Republic of China
The conventional fault models of PLAs are crosspoint, stuck-at and bridging fault models. Many techniques for PLA testing based on these fault models have been proposed in the past. However, these techniques cannot be...
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The conventional fault models of PLAs are crosspoint, stuck-at and bridging fault models. Many techniques for PLA testing based on these fault models have been proposed in the past. However, these techniques cannot be applied to the break fault model due to the memory behaviour. Unfortunately, it has been shown that break faults occur frequently. Thus, considering a break fault model is important to enhance the quality of PLA testing. The behaviour of break faults in PLAs is analysed in detail and a complete PLA break fault ATPG system, PLABEK, is proposed. PLABEK contains four main parts: break fault collapsing;pruning algorithm based test pair generation;serial-fault-injection parallel-bit-operation event-driven break fault simulation;and testability-measure-based fault ordering. Experimental results show that PLABEK can generate very compact complete test sequences for break faults of PLAs very fast.
In this paper we present the programmablelogic array (PLA) topological optimization problem using folding techniques. First of all, we consider a multiple unconstrained column folding and solve this problem using the...
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In this paper we present the programmablelogic array (PLA) topological optimization problem using folding techniques. First of all, we consider a multiple unconstrained column folding and solve this problem using the Simulated Annealing (SA) algorithm. Afterwards we extend this algorithm in order to solve several types of constrained folding problem. In this way, simple folding is considered as a special case of multiple constrained folding. Bipartite graphs are used to solve the multiple constrained folding problem. Finally, we give some experimental results found by executing the algorithm.
In this paper, we present a new graph model and an associated set of operations for representing programmable logic arrays (PLA's), The signal lines and devices of a PLA are represented as the edges and vertices o...
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In this paper, we present a new graph model and an associated set of operations for representing programmable logic arrays (PLA's), The signal lines and devices of a PLA are represented as the edges and vertices of a directed graph, respectively, Through this graph model, most realistic PLA faults, including cross-point, stuck-at, break, and bridging faults, can be modeled and classified, and the maximal diagnosis resolution of a PLA can be determined. Moreover, the model can be easily transformed into a gate-level model, Hence, the work of automatic test-pattern generation for a PLA and for other random logic can be done simultaneously. We also show that this representation can be extended to some logic design techniques such as logic minimization, folding, and decomposition for PLA's, Thus, this graph model can unify the data structure and operations required in PLA design and test.
Conventional programmable logic arrays (PLAs) implement both the AND and OR logic planes with dynamic NOR gates. They are fast, regular in structure and easy to program. However, they have high power dissipation and s...
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Conventional programmable logic arrays (PLAs) implement both the AND and OR logic planes with dynamic NOR gates. They are fast, regular in structure and easy to program. However, they have high power dissipation and suffer from an inherent timing race that increases design effort, reduces circuit robustness in the presence of variations, and adversely impacts performance. In this paper, a PLA which implements the AND plane as a hierarchical combination of dynamic NAND gates and retains the dynamic NOR gate based OR plane is presented. The NAND-NOR PLA architecture completely eliminates the critical timing race between the logic planes and has significantly lower power dissipation than the conventional PLA. Simulated energy-delay product of an optimized design on a foundry 130 nm low standby power process shows that the proposed circuit architecture has 43% lower energy-delay product than the conventional MA design. The fabricated circuits have been tested fully functional on silicon demonstrating a maximum operating frequency or 1.61 GHz;at V-DD = 1.6 V.
Shows a method of designing programmable logic arrays (PLAs) using multiple-valued input, two-valued output functions (MVITVOFs). A MVITVOF is an extension of the two-valued logic function. An expression for a MVITVOF...
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Shows a method of designing programmable logic arrays (PLAs) using multiple-valued input, two-valued output functions (MVITVOFs). A MVITVOF is an extension of the two-valued logic function. An expression for a MVITVOF directly represents a multiple-output PLA with decoders. Each product of the expression corresponds to each column of the PLA, so the number of products; in the expression equals the number of columns of the PLA. The array size of the PLA is proportional to the number of products; the PLA can thus be minimized by minimizing the expression
Implementing a function using a programmablelogic array (PLA) can often be very expensive in terms of area. Folding rows and/or columns of a PLA usually leads to a reduction in area. In this paper the problem of faul...
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Implementing a function using a programmablelogic array (PLA) can often be very expensive in terms of area. Folding rows and/or columns of a PLA usually leads to a reduction in area. In this paper the problem of fault detection in folded PLAs is considered. A new fault, the ‘cutpoint’ fault, is described and universal test sets for the detection of this fault are presented. Modifications to existing built-in universally testable design techniques for nonfolded PLAs are presented; the new designs are now applicable to folded PLAs.
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