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检索条件"主题词=Programmable logic arrays"

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Maximum current estimation in programmable logic arrays

Maximum current estimation in programmable logic arrays

引用

Great Lakes Symposium on VLSI

作者： S. Bobba I.N. Hajj Coordinated Science Lab & ECE Dept University of Illinois Urbana-Champaign Urbana IL USA

programmable logic array (PLA) is a circuit realization for the two-level sum of products representation of a multi-output Boolean function. The current drawn by a PLA is input dependent and it makes the problem of estimating the maximum current intractable. Integrated circuit reliability and signal integrity are related to the maximum current drawn by the circuit. Hence, an estimate of the maximum current is required for the design of a reliable VLSI circuit. In this paper, we present an input pattern-independent algorithm to obtain the estimate of maximum and minimum currents drawn by a PLA over all possible input vectors. Experimental results on several benchmark circuits and comparisons with exhaustive simulations are also included in this paper.

关键词： programmable logic arrays Integrated circuit reliability logic circuits Boolean functions Very large scale integration Circuit simulation

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On Yield Consideration for the Design of Redundant programmable logic arrays

On Yield Consideration for the Design of Redundant Programma...

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Design Automation Conference

作者： Chin-Long Wey Department of Electrical Engineering Michigan State University East Lansing MI USA

This paper presents the design of a programmable logic array with redundancy. The design allows for the repair of a defective chip by including the redundancy circuits to a conventional PLA. When the redundancy technique is implemented into the VLSI or WSI chip design, the increased cost is proportional to the increased chip silicon area. Indeed, the additional spare lines may increase the silicon area and propagation delay. However, if the provided redundancy can be efficiently utilized to repair the defective chip, then the additional spare lines may increase rather decrease the chip yields. The objective of the present paper is to analyze the possibility of yield enhancement rhrough redundant design.

关键词： programmable logic arrays logic design Redundancy Circuit faults Very large scale integration Manufacturing Permission logic testing Silicon Built-in self-test

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PLABEK: a complete automatic test pattern generation system for break faults in programmable logic arrays

PLABEK: a complete automatic test pattern generation system ...

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International Symposium on VLSI Technology, Systems and Applications

作者： Gwo-Haur Hwang Wen-Zen Shen Shing Tenqchen VLSI Support Center Telecommunications Laboratories Taoyuan Taiwan National Chiao Tung University Hsinchu Taiwan

ISBN: (纸本)078032773X

In this paper, a complete PLA break fault ATPG system, PLABEK, is proposed. PLABEK contains four main parts: 1) break fault collapsing; 2) pruning algorithm based test pair generation; 3) serial-fault-injection parallel-bit-operation event-driven break fault simulation; and 4) testability-measure-based fault ordering. Experimental results show that PLABEK can generate complete compact test sequences for PLA's break faults very fast.

关键词： Automatic test pattern generation Automatic logic units programmable logic arrays programmable logic devices logic testing Circuit faults Fault detection Semiconductor device modeling Very large scale integration Circuit testing

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A crosstalk minimization technique for sublithographic programmable logic arrays

A crosstalk minimization technique for sublithographic progr...

引用

IEEE Conference on Nanotechnology

作者： Harika Manem Garrett S. Rose Department of Electrical and Computer Engineering Polytechnic University Brooklyn NY USA

ISBN: (纸本)9781424448326

The emergence of alternative technologies due to continued technology migration into the nanometer regime has led to the design of several novel logic and memory architectures. These architectures, in particular array based architectures built from crossbar structures, aim to achieve higher logic/memory densities with lower power consumption and acceptable delays as compared to present day CMOS technology. However crosstalk induced in these nanoscale arrays limits the minimum wire spacing realizable and thereby the logic density that can be achieved. In this work we analyze the crosstalk produced in sublithographic programmable logic array (PLA) architectures and propose an alternative layout scheme that reduces the effects of crosstalk in adjacent wires. The proposed methodology has an interleaved layout scheme with two non-overlapping out-of-phase clocks that prevent neighboring wires from transitioning simultaneously. Results presented in this paper indicate that this scheme provides for better tolerance against crosstalk than other structures proposed for sublithographic PLAs. The effects of different parasitics (i.e. coupling and decoupling capacitances from different parts of the crossbar segment) on the crosstalk induced are also analyzed.

关键词： programmable logic arrays Crosstalk Minimization CMOS logic circuits logic arrays CMOS technology Wires logic design Memory architecture Energy consumption

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BIST-PLA: A Built-In Self-Test Design of Large programmable logic arrays

BIST-PLA: A Built-In Self-Test Design of Large Programmable ...

引用

Design Automation Conference

作者： Chun-Yeh Liu K.K. Saluja J.S. Upadhyaya Department of Electrical and Computer Engineering University of Wisconsin Madison Madison WI USA Department of Electrical and Computer Engineering State University of New York University at Buffalo Buffalo NY USA

A new method for designing a Built-In Self-Test programmable logic Array (BIST-PLA) is presented. In the proposed design, the Test Pattern Generator and the Response Evaluator circuits are very simple. The design requires a rearrangement of the AND (OR) planes on the basis of number of crosspoints in the product (output) lines in the PLA. The BIST-PLA proposed in this paper is capable of detecting all single stuck-at and crosspoint faults and almost all multiple faults, thus offering fault coverage higher than any of the known BIST designs of PLAs. A program has been written which generates a BIST-PLA. The program was used to study 22 large PLAs from the list of 56 PLAs given in [18]. It was found that the silicon area overhead for almost all these PLAs was lower than those using methods reported in literature [10] [11] [12] [13] [14] [15] [16] [17]. Furthermore, the delay performance degradation was found to be within acceptable limits. The program was developed in the unix environment (4.3beta BSD UNIX) and is integratable with the existing design automation tools.

关键词： programmable logic arrays Built-in self-test logic design Circuit faults Design methodology Test pattern generators Electrical fault detection Fault detection Silicon Delay

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High Speed programmable logic arrays in ESFI MOS Technology

High Speed Programmable Logic Arrays in ESFI MOS Technology

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European Conference on Solid-State Circuits (ESSCIRC)

作者： E Hebenstreit K H Horninger Siemens Research and Technology Laboratories Munich Germany

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Dynamic techniques for yield enhancement of field programmable logic arrays

Dynamic techniques for yield enhancement of field programmab...

引用

IEEE International Test Conference

作者： M. Demjanenko S.J. Upadhyaya Department of Electrical and Computer Engineering State University of New York University at Buffalo Buffalo NY USA

Two techniques are presented to increase the effective yield of field programmable logic arrays (FPLAs). In the first technique, a reconfiguration scheme is proposed to dynamically alter the product-term allocation of the mask PLA onto the product lines of the raw FPLA once a type-two fault is diagnosed. This technique does not require any extra product lines to obtain a usable destination FPLA. The second technique utilizes the often unused product lines within the FPLA. It is shown that once an error is detected during the programming procedure, a product line can always be desensitized from the rest of the FPLA. The intended product term is then simply reprogrammed onto one of the extra product lines.< >

关键词： programmable logic arrays Fuses Circuit faults Hardware Redundancy Reconfigurable logic Costs Testing Computer aided manufacturing Semiconductor device measurement

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An expert system for incorporating design for testability in programmable logic arrays

An expert system for incorporating design for testability in...

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IEEE Southeastcon

作者： N. Yousuf K.-H. Chang Computer Science and Engineering Department Aubum University Auburn AL USA

The task of designing reliable very large-scale integrated (VLSI) chips is difficult, due to the small device geometries. This situation forces the designers to incorporate testability as part of design. Numerous techniques for incorporating testability in programmable logic arrays have been evolved. The selection of a testability technique which is viable for a particular design requires much decision making. Thus there is a potential of effectively utilizing the decision-making capabilities of an expert system in this domain. Here, an expert system which selects a testability technique for a given design and generates a modified version is presented.< >

关键词： programmable logic arrays Expert systems Design for testability logic design logic testing System testing Very large scale integration logic devices Circuit testing User interfaces

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HAMLET-an expression compiler/optimizer for the implementation of heuristics to minimize multiple-valued programmable logic arrays

HAMLET-an expression compiler/optimizer for the implementati...

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International Symposium on Multiple-Valued logic

作者： J.M. Yurchak J.T. Butler Department of Computer Sciences Naval Postgraduate School Monterrey CA USA Department of Electr and Computer Engineering Naval Postgraduate School Monterrey CA USA

A description is given of HAMLET, a CAD tool written in C, that translates a user specification of a multiple-valued expression into a layout of a multiple-valued programmable logic array (MVL-PLA) which realizes that expression. It is modular to accommodate future minimization heuristics and future MVL-PLA technologies. At present, it implements two heuristics and one MVL-PLA technology, current-node CMOS. Specifically, HAMLET accepts a sum-of-products expression from the user, applies a minimization heuristic, and then produces a PLA layout of a multiple-valued current-mode CMOS PLA. In addition to its design capabilities, HAMLET can analyze heuristics. Random functions can be generated, heuristics applied, and statistics computed on the results. User-derived expressions can also be analyzed. In addition to the minimization heuristics, HAMLET can apply search strategies based on these heuristics, which, in the extreme, are exhaustive, producing true minimal forms.< >

关键词： Optimizing compilers Minimization methods Circuits Heuristic algorithms Laboratories programmable logic arrays

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A Couple of ECL Laser and Mask programmable logic arrays

A Couple of ECL Laser and Mask Programmable Logic Arrays

引用

European Conference on Solid-State Circuits (ESSCIRC)

作者： C. Barre W. Brackelmann V. Koch J. Kirbach Siemens AG Munchen Germany

A high speed (3 ns typ.) laser customized programmable logic array and a compatible mask programmable logic array will be described. The organisation is 36 + 16 feedback × 48 × 16 with 16 flipflops offering serial scan diagnostic capability. They have ECL 100K logic levels and are packed in a 64 pin package. The FPLA has on chip self testing circuitry.

关键词： programmable logic arrays Optical coupling Optical arrays Circuit testing Laser feedback logic programming Packaging Automatic testing logic testing System testing

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